div.v

来自「包含跳转」· Verilog 代码 · 共 58 行

`timescale 1ns/1ps
module div(quot,remd,DIV1_in,DIV2_in,DIVLE);
    output[7:0] quot;
    output[7:0] remd;
    input[7:0] DIV1_in;
    input[7:0] DIV2_in;
    input DIVLE;
    
    reg[7:0] quot;
    reg[7:0] remd;
   
   reg [7:0] tempa;
   reg [7:0] quotient;
   reg  [7:0] remainder;
   reg [2:0] index;


   
   always @(DIV1_in or DIV2_in or DIVLE)
   if(DIVLE=='b0)
    begin
        quot='b0;
        remd='b0;
    end
    else
   begin
       tempa = DIV1_in;
       quotient = 8'b0;
       remainder = 8'b0;
       index = 7;
       repeat(8)
       begin
           remainder = {remainder[7:1],tempa[7]};
                    
           if (remainder>=DIV2_in) 
          	 begin
              		 remainder=remainder-DIV2_in;
              		 quotient[index]=1;
           	 end
           else
           	begin
              		quotient[index]=0;
           	end
           tempa = (tempa << 1);
           remainder = (remainder << 1);
           index=index-1;
       end
       remainder = (remainder >> 1);
       if(DIV1_in < DIV2_in)
       	remainder[7] = 1;
       	else
       	remainder[7] = 0;
   	   {quot,remd} = {quotient,remainder};
   end
   
  
endmodule