cu.v

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`timescale 1ns/1ps
module CU (CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,PCCE,MUL1LE,MUL2LE,MUL3LLE,MUL3HLE,MULLE,
DIV1LE,DIV2LE,DIVLE,QUOTLE,REMDLE,mux_C_sel,mux_DB_sel,mux_AB_sel,CS,READ,WRITE,clk,reset,C_in,Z_in,IR_in);
    parameter FIRST='b00,SECOND='b01,THIRD='b10,HLT='b11;
    
    output CLE;  reg CLE;
    output ZLE;  reg ZLE;
    output ACLE;  reg ACLE;
    output GRLE;  reg GRLE;
    output ARLE;  reg ARLE;
    output IRLE;  reg IRLE;
    output PCLE;  reg PCLE;
    output PCCE;  reg PCCE;
    output MUL1LE; reg MUL1LE;
    output MUL2LE; reg MUL2LE;
    output MUL3LLE;reg MUL3LLE;
    output MUL3HLE;reg MUL3HLE;
    output MULLE;  reg MULLE;
	 output DIV1LE; reg DIV1LE;
	 output DIV2LE; reg DIV2LE;
	 output DIVLE;  reg DIVLE;
	 output QUOTLE; reg QUOTLE;
	 output REMDLE; reg REMDLE;
    
    output[4:0] ALU_OP; reg[4:0] ALU_OP;
    output[2:0] GR_address; reg[2:0] GR_address;
    output[1:0] mux_C_sel;  reg[1:0] mux_C_sel;
    output[2:0] mux_DB_sel; reg[2:0] mux_DB_sel;
    output mux_AB_sel;      reg mux_AB_sel;
    output WRITE;           reg WRITE;
    output CS;              reg CS;
    output READ;            reg READ;
    
    input clk;
    input reset;
    input C_in;
    input Z_in;
    input [7:0] IR_in;
    
    reg [1:0] state;
    
    always @(posedge clk or negedge reset)
    begin
        if(!reset)
        state<=FIRST;
        else 
        begin
            case(state)
                FIRST:state<=SECOND;
                SECOND:state<=THIRD;
                THIRD:
                begin 
                if(IR_in[7:3]=='b01111)
                state<=HLT;
                else
                state<=FIRST;
                end
                HLT:state<=HLT;
            endcase
        end
    end

   always @(state or C_in or Z_in or IR_in)
    begin
        CLE='b0;
        ZLE='b0;
        ALU_OP='b0;
        ACLE='b0;
        GR_address='b0;
        GRLE='b0;
        IRLE='b0;
        ARLE='b0;
        PCLE='b0;
        PCCE='b0;
        
        MUL1LE='b0;
        MUL2LE='b0;
        MULLE='b0;
        MUL3LLE='b0;
        MUL3HLE='b0;
		  DIV1LE='b0;
		  DIV2LE='b0;
		  REMDLE='b0;
		  DIVLE='b0;
		  QUOTLE='b0;
		  READ='b1;
		  WRITE='b1;
		  CS='b0;
		  
		  
        mux_C_sel='b0;
        mux_DB_sel=3'b00;
        mux_AB_sel='b0;
        
        
        case(state)
            FIRST:
            begin
                mux_AB_sel='b0;
                mux_DB_sel='b10;
                IRLE='b1;
                PCCE='b1;
                READ=0;
            end

            SECOND:
            begin 
            case(IR_in[7:3])
            'b00000,
            'b00001:
                begin
                    mux_AB_sel='b0;
                    mux_DB_sel='b10;
                    PCCE='b1;
                    ARLE='b1;
                    READ=0;
                end
                    
                    
            'b00010:
                    begin
                        GR_address=IR_in[2:0];
                        ALU_OP=IR_in[7:3];
                        mux_DB_sel='b01;
                        GRLE='b1;
                        CLE='b1;
                        ZLE='b1;
                        CS=1;
                    end
                    
                    
            'b00011,
            'b00100,
            'b00101,
            'b00110,
            'b00111,
            'b01000,
            'b01001,
            'b01010,
            'b01011:
                    begin
                        GR_address=IR_in[2:0];
                        ALU_OP=IR_in[7:3];
                        mux_DB_sel='b01;
                        ACLE='b1;
                        CLE='b1;
                        ZLE='b1;
                        CS=1;
                        
                        if(IR_in[7:3]=='b01010)
                          mux_C_sel='b10;
                        if(IR_in[7:3]=='b01011)
                          mux_C_sel='b01;
                      end
                      
                      
                'b01100,
                'b01101,
                'b01110:
                      begin
                          mux_AB_sel='b0;
                          mux_DB_sel='b10;
                          READ=0;
                          case(IR_in[4:3])
                              'b00:PCLE='b1;
                              'b01:begin PCLE=!Z_in;PCCE='b1;end
                              'b10:begin PCLE=!C_in;PCCE='b1;end
                          endcase
                      end
                'b10000,
                'b10001:
                begin
                    ARLE=1;
                    mux_AB_sel=0;
                    mux_DB_sel=3'b010;
                    PCCE=1;
                    READ=0;
                end
                'b10010:
                begin
                    MULLE='b1;
                    MUL3LLE='b1;
                    MUL3HLE='b1;
                end
                'b10011,
                'b10100,
					 'b10101,
					 'b10110,
					 'b11000,
					 'b11001:
		          begin
                    ARLE=1;
                    mux_DB_sel='b010;
                    mux_AB_sel=0;
                    PCCE=1;
                    READ=0;
                    
                end
					 'b10111:
					 begin
					     DIVLE=1;
						  QUOTLE=1;
						  REMDLE=1;
					 end
                
                  endcase
              end
              
              
              THIRD:
              begin
                  case(IR_in[7:3])
                      'b00000,
                      'b00001:
                      begin
                      mux_AB_sel='b1;
                      if(!IR_in[3])
                      begin
                          mux_DB_sel=3'b10;
                          ACLE='b1;
                      end
                      else begin
                          mux_DB_sel=3'b000;
                          WRITE='b0;
                           end
                       end
                      'b10000,
                      'b10001:
                      begin
                      mux_AB_sel='b1;
                      READ=0;
                      if(!IR_in[3])
                      begin
                          mux_DB_sel=3'b010;
                          MUL1LE=1;
                      end
                      else begin
                          mux_DB_sel=3'b010;
                          MUL2LE=1;
                            end
                       end
                       'b10011,
                       'b10100:
                       begin
                           mux_AB_sel='b1;
                           WRITE=0;
                           if(IR_in[3])
                           begin
                               mux_DB_sel=3'b011;
                            end
                            else mux_DB_sel=3'b100;
                        end
								'b10101,
								'b10110:
								begin
								    mux_AB_sel='b1;
									 mux_DB_sel='b010;
									 READ=0;
									 
									 if(IR_in[3])
									 begin
									    DIV1LE=1;
									 end
									 else DIV2LE=1;
								end	
								
                        'b11000,
                        'b11001:
                        begin
                            mux_AB_sel=1;
                            
                            WRITE=0;
                            if(IR_in[3])
                               mux_DB_sel='b110;
                            else mux_DB_sel='b101;
                        end
                        							
                endcase
              end
      endcase
  end
  endmodule