cpu.v

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`timescale 1ns/1ps
module CPU(data_out,address_out,CS,READ,WRITE,clk,reset);
    parameter width=8;         
    inout[width-1:0] data_out;//??????
    output[7:0] address_out;  //??????
    output CS;
    output READ;
    output WRITE;                //????
    
    wire[width-1:0] data_in;//??????
    input clk;               //??
    input reset;             //????
    wire[width-1:0] data_bus;//????
    wire[width-1:0] ALU_out;//??ALU??????
    wire[width-1:0] GR_out;//???????????
    wire[7:0] IR_out;      //???????????
    wire[7:0] AC_out;      //?????????
    wire[7:0] MUL1_out;
    wire[7:0] MUL2_out;
    wire[7:0] MUL3L_out;
    wire[7:0] MUL3H_out;
    wire[7:0] MULL_out;
    wire[7:0] MULH_out;
    wire[7:0] DIV1_out;
    wire[7:0] DIV2_out;
	 wire[7:0] quot;
	 wire[7:0] remd;
	 wire[7:0] QUOT_out;
	 wire[7:0] REMD_out;
	 
	
	 
    
    wire is_zero; //Z????????
    wire C_out;   //C????????
    wire C_in;    //C????????
    wire Z_out;   //Z????????
    
    wire[7:0] AR_address;  //???????????
    wire[7:0] PC_address;  //PC??????
    wire[2:0] GR_address;  //?????????
    wire[4:0] ALU_OP;      //ALU??????
    wire[1:0] mux_C_sel;   //C??????????????
    wire[2:0] mux_DB_sel;  //????DB?????????
    wire mux_AB_sel;
    
    wire CLE;    //C???????
    wire ZLE;    //Z???????
    wire IRLE;   //IR??
    wire ARLE;   //AR??
    wire ACLE;   //AC??
    wire GRLE;   //???????
    wire PCLE;   //PC????
    wire PCCE;   //PC????
    wire ALU_C;  //ALU?????
    wire MUL1LE;
    wire MUL2LE;
	 wire MUL3LLE;
	 wire MUL3HLE;
	 wire MULLE;
	 wire DIV1LE;
	 wire DIV2LE;
	 wire DIVLE;
	 wire QUOTLE;
	 wire REMDLE;
	 
    
    
    assign data_in=data_out; 
    //???????
    assign data_out=(~WRITE & ~CS)?data_bus:'bzzzzzzzz;   //???????
    assign is_zero=(ALU_out=='b0)?'b1:'b0;   //??0???
    
    //clock clock(clk);
    
    register #(1) C (.register_out(C_out),.register_in(C_in),.clk(clk),.reset(reset),.load_enable(CLE));
    //??C?????
    register #(1) Z (.register_out(Z_out),.register_in(is_zero),.clk(clk),.reset(reset),.load_enable(ZLE));
    //??Z?????
    register #(8) IR (.register_out(IR_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(IRLE));
    //???????
    register #(8) AR (.register_out(AR_address),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(ARLE));
    //???????
    register #(8) MUL1 (.register_out(MUL1_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(MUL1LE));
    //???????
    register #(8) MUL2 (.register_out(MUL2_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(MUL2LE));
    //???????
	 register #(8) MUL3L (.register_out(MUL3L_out),.register_in(MULL_out),.clk(clk),.reset(reset),.load_enable(MUL3LLE));
    //???????
	 register #(8) MUL3H (.register_out(MUL3H_out),.register_in(MULH_out),.clk(clk),.reset(reset),.load_enable(MUL3HLE));
    //???????
	 register #(8) DIV1 (.register_out(DIV1_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(DIV1LE));
    
    register #(8) DIV2 (.register_out(DIV2_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(DIV2LE));
    
    register #(8) QUOT (.register_out(QUOT_out),.register_in(quot),.clk(clk),.reset(reset),.load_enable(QUOTLE));
    //?????
    
	 register #(8) REMD (.register_out(REMD_out),.register_in(remd),.clk(clk),.reset(reset),.load_enable(REMDLE));
    //?????
	 
	 register #(8) AC (.register_out(AC_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(ACLE));
    //?????
	 
    mux4 #(1) mux_C (.mux4_out(C_in),.m0_in(ALU_C),.m1_in(AC_out[0]),.m2_in(AC_out[7]),.m3_in(1'b0),.sel_in(mux_C_sel));
    //??C????????
    mux8 #(8) mux_DB (.mux8_out(data_bus),.m0_in(AC_out),.m1_in(ALU_out),.m2_in(data_in),.m3_in(MUL3L_out),.m4_in(MUL3H_out),.m5_in(QUOT_out),.m6_in(REMD_out),.m7_in(8'b0),.sel_in(mux_DB_sel));
    //???????????'b00??AC?'b01??ALU_O,'b10??????
    mux2 #(8) mux_AB (.mux2_out(address_out),.m0_in(PC_address),.m1_in(AR_address),.sel_in(mux_AB_sel));
    //???????????'b0??PC,'b1??AR?
    
    GR GR (.GR_out(GR_out),.GR_in(data_bus),.clk(clk),.reset(reset),.GR_address(GR_address),.load_enable(GRLE));
    //????????
    
    ALU ALU (.ALU_O(ALU_out),.ALU_C(ALU_C),.C_in(C_out),.op(ALU_OP),.AC_in(AC_out),.GR_in(GR_out));
    //??ALU
    
    PC PC (.pc_out(PC_address),.pc_in(data_bus),.clk(clk),.reset(reset),.load_enable(PCLE),.count_enable(PCCE));
    //???????
    
    CU CU (.CLE(CLE),.ZLE(ZLE),.ALU_OP(ALU_OP),.ACLE(ACLE),.GR_address(GR_address),.GRLE(GRLE),.IRLE(IRLE),.ARLE(ARLE),
    .PCLE(PCLE),.PCCE(PCCE),.MUL1LE(MUL1LE),.MUL2LE(MUL2LE),.MUL3LLE(MUL3LLE),.MUL3HLE(MUL3HLE),.MULLE(MULLE),
	 .DIV1LE(DIV1LE),.DIV2LE(DIV2LE),.DIVLE(DIVLE),.QUOTLE(QUOTLE),.REMDLE(REMDLE),.mux_C_sel(mux_C_sel),.mux_DB_sel(mux_DB_sel),.mux_AB_sel(mux_AB_sel),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset),
    .C_in(C_out),.Z_in(Z_out),.IR_in(IR_out));
    //?????

	 MUL MUL(.MULL_out(MULL_out),.MULH_out(MULH_out),.MUL1_in(MUL1_out),.MUL2_in(MUL2_out),.MULLE(MULLE));     
    
	 
	 div div(.quot(quot),.remd(remd),.DIV1_in(DIV1_out),.DIV2_in(DIV2_out),.DIVLE(DIVLE));
	 
endmodule