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counter.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
counter.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
testbench.v
`timescale 1ns/1ns
module testbench;
reg clk;
reg rst;
reg codein;
wire [1:0] codeoutv;
wire [1:0] codeoutb;
initial
begin
clk
decode.v
module decode(clk,rst,codein,codeoutv,codeoutb);
input clk,rst;
input codein;
output [1:0] codeoutv;
output [1:0] codeoutb;
reg [2:0] count0;
reg [2:0] count01;
reg [4:0] count11;
reg [1:0] codeoutv,
infifo.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
clock.v
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006-2009 (c) Lpstar Corporation
// ALL RIGHTS RESERVED
srt.v
//Radix-2 SRT Verilog Code
module SRT(Dividend,Divisor,Quotient,Remainder);
input [7:0]Dividend;
input [3:0]Divisor;
output [4:0]Quotient;
output [8:0]Remainder;
evm.v
`timescale 1ns / 1ps
module vote(clk,led,butt);
input clk;
output [15:0] led;
input [0:6] butt;
reg [15:0] led;
reg [7:0] votes;
reg [7:0] count_a,count_b,count_c,coun
alu.v
`timescale 1ns/1ps
module ALU(ALU_O,ALU_C,C_in,op,AC_in,GR_in);
parameter width=8;
output ALU_C;
output [width-1:0] ALU_O;
input C_in;
input [4:0] op;
input [width-1:0] AC_in;