mul.v

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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    11:20:43 12/13/06
// Design Name:    
// Module Name:    MUL
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module MUL(MULL_out,MULH_out,MUL1_in,MUL2_in,MULLE);
input[7:0] MUL1_in;
input[7:0] MUL2_in;
input MULLE;
output[7:0] MULL_out;
output[7:0] MULH_out;
reg[7:0] MULL_out;
reg[7:0] MULH_out;


always @(MULLE or MUL1_in or MUL2_in)
begin
    if(MULLE==0)
    {MULH_out,MULL_out}=0;
    else
    {MULH_out,MULL_out}=MUL1_in*MUL2_in;
end





endmodule