latch_8.v

来自「verilog HDL example .many module .」· Verilog 代码 · 共 12 行

module latch_8(qout,data,clk);
output[7:0] qout;
input[7:0] data;
input clk;
reg[7:0] qout;

always @(clk or data)
begin
if (clk) qout<=data;
end
endmodule