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V 的代码
lp_tx_top_cyclone.v
module lp_tx_top_cyclone (clk,
rst_n,
tvere,
tx_wr,
tx_wdata,
tx_wrused,
tx_wrfull,
clk_out,
data_out,
acki,
bcmpo_n
);
ddr_clk.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
lp_rx.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
lp_tx.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
tx_test_harness.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
rx_test_harness.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
strip.tests
v=`echo "" ; echo "" ; echo ""`
echo "'$v'"
v=`echo -n " ab "`
echo "'$v'"
v=`echo -n " "`
echo "'$v'"
v=`echo -n ""`
echo "'$v'"
v=`echo ""`
echo "'$v'"
v=`echo`
echo "'$v'"
v=`echo ababababababab`
e
glbl.v
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire
float_add_modue_synthesis.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
/////////////////////////////////////////////////////////
test_test.v
module float_add_module
(
input CLK, RSTn,
input [31:0]A,B,
output [31:0]Result,
input Start_Sig,
output [3:0]Done_Sig,
/*****************/
output [56:0]SQ_rA,SQ_rB,
output [48:0]SQ_Temp,SQ_Te