des.v

Verilog实现的DES和3-DES

/*-----------------------------------------------------------------------
/Module			:	DES
/Filename		:	DES.v
/Description		:	DES cell
/Called by		:	DES
/Simulator		:	Modelsim5.7 and  Simvision / WindowsXP
/Synthesis tool		:	Synplify / WindowsXP
/Revision history	:	2008-05-30 v1.0

--------------------------------------------------------------------------*/




module DES(
		clk,
		rst_n,
		sw_rst,
		//buff_out_load,
		//Left_first,
		buffin,
		buffo,
		key_321,
		work_mode,
		s_width,
		DES_encrypt_start,
		DES_decrypt_start,
		//DES3_encrypt_start,
		//DES3_decrypt_start,
		load_data,
		load_key,
		load_iv,
		ready
		
);
input 	clk;				//systerm clk
input 	rst_n;				//reset signal
input 	sw_rst;				//soft reset signal
input 	[2:0] key_321;			//how many keys
input	[4:0] s_width;			//the width of s bit
//input	buff_out_load;				//read enable signal
//input	Left_first;			//load low bits data first
input 	load_data;			//load data enable signal
input 	load_key;			//load key enable signal
input 	load_iv;			//load iv enable signal
input 	[4:0] work_mode;		//work mode of des
input  	DES_encrypt_start;		//des encipher plaintext start signal
input   DES_decrypt_start;		//des decipher cipertext start signal
//input   DES3_encrypt_start;		//3des encipher plaintext start signal
//input   DES3_decrypt_start;		//3des decipher cipertext start signal
input [31:0] buffin;			//the bus of input data

output 	ready;				//des finish signal
output [63:0] 	buffo;			//the bus of output data

DES_CTRL 	U_DES_CTRL(
				.clk			(clk			),				
				.rst_n			(rst_n			),
				.sw_rst			(sw_rst			),
				.key_321		(key_321		),
				.work_mode		(work_mode		),
				.s_width		(s_width		),
				.DES_encrypt_start	(DES_encrypt_start	),
				.DES_decrypt_start	(DES_decrypt_start	),
				//.DES3_encrypt_start	(DES3_encrypt_start	),
				//.DES3_decrypt_start	(DES3_decrypt_start	),
				.load_data		(load_data		),
				.load_key		(load_key		),
				.load_iv		(load_iv		),
				//.buff_out_load                    (buff_out_load			),
				//.Left_first		(Left_first		),
				.ready			(ready			),
				.lut_en			(lut_en			),
	        		.ls1(ls1),.ls2(ls2),.ls3(ls3),.ls4(ls4),.ls5(ls5),.ls6(ls6),.ls7(ls7),.ls8(ls8),
				.ls9(ls9),.ls10(ls10),.ls11(ls11),.ls12(ls12),.ls13(ls13),.ls14(ls14),.ls15(ls15),.ls16(ls16),
	        		.dls2(dls2),.dls3(dls3),.dls4(dls4),.dls5(dls5),.dls6(dls6),.dls7(dls7),.dls8(dls8),
				.dls9(dls9),.dls10(dls10),.dls11(dls11),.dls12(dls12),.dls13(dls13),.dls14(dls14),.dls15(dls15),.dls16(dls16),
	        		.IP			(IP 			),
				.data_sel_iv		(data_sel_iv		),
				.data_sel_buff		(data_sel_buff		),
				.data_sel_com1		(data_sel_com1		),
				.data_sel_com2		(data_sel_com2		),
				.k1_sel_key1		(k1_sel_key1		),
				.k2_sel_key2		(k2_sel_key2		),
				.k3_sel_key3		(k3_sel_key3		),
				.key_sel_k1		(key_sel_k1		),
				.key_sel_k2		(key_sel_k2		),
				.key_sel_k3		(key_sel_k3		),
				.iv_sel_tmp		(iv_sel_tmp		),
				.iv_sel_data		(iv_sel_data		),
				.tmp_sel_buff		(tmp_sel_buff		),
				.IP_1			(IP_1			),
				.buff_xor_iv		(buff_xor_iv		),
				.data_xor_iv		(data_xor_iv		),
				.tmp_xor_data_1		(tmp_xor_data_1		),
				.tmp_xor_data_8		(tmp_xor_data_8		),
				.tmp_xor_data_16	(tmp_xor_data_16	),
				.tmp_xor_data_32	(tmp_xor_data_32	),
				.tmp_xor_data_64	(tmp_xor_data_64	),
				.iv_shift_1		(iv_shift_1		),
				.iv_shift_8		(iv_shift_8		),
				.iv_shift_16		(iv_shift_16		),
				.iv_shift_32		(iv_shift_32		),
				.iv_shift_64		(iv_shift_64		),
				.iv_back_tmp		(iv_back_tmp		),
				.buff_load		(buff_load		),
				.buff_load_low		(buff_load_low		),
				.iv_load		(iv_load		)
				//.sel_left		(sel_left		),
				//.sel_right		(sel_right		)
				);
				

DES_CAL		U_DES_CAL(
				.clk			(clk			),
				.rst_n			(rst_n			),
				.sw_rst			(sw_rst			),
				.buffin			(buffin			),
				.buffo			(buffo			),
				//.Left_first		(Left_first		),
				.lut_en			(lut_en			),
	        		.ls1(ls1),.ls2(ls2),.ls3(ls3),.ls4(ls4),.ls5(ls5),.ls6(ls6),.ls7(ls7),.ls8(ls8),
				.ls9(ls9),.ls10(ls10),.ls11(ls11),.ls12(ls12),.ls13(ls13),.ls14(ls14),.ls15(ls15),.ls16(ls16),
	        		.dls2(dls2),.dls3(dls3),.dls4(dls4),.dls5(dls5),.dls6(dls6),.dls7(dls7),.dls8(dls8),
				.dls9(dls9),.dls10(dls10),.dls11(dls11),.dls12(dls12),.dls13(dls13),.dls14(dls14),.dls15(dls15),.dls16(dls16),
	        		.IP			(IP 			),
				.data_sel_iv		(data_sel_iv		),
				.data_sel_buff		(data_sel_buff		),
				.data_sel_com1		(data_sel_com1		),
				.data_sel_com2		(data_sel_com2		),
				.k1_sel_key1		(k1_sel_key1		),
				.k2_sel_key2		(k2_sel_key2		),
				.k3_sel_key3		(k3_sel_key3		),
				.key_sel_k1		(key_sel_k1		),
				.key_sel_k2		(key_sel_k2		),
				.key_sel_k3		(key_sel_k3		),
				.iv_sel_tmp		(iv_sel_tmp		),
				.iv_sel_data		(iv_sel_data		),
				.tmp_sel_buff		(tmp_sel_buff		),
				.IP_1			(IP_1			),
				.buff_xor_iv		(buff_xor_iv		),
				.data_xor_iv		(data_xor_iv		),
				.tmp_xor_data_1		(tmp_xor_data_1		),
				.tmp_xor_data_8		(tmp_xor_data_8		),
				.tmp_xor_data_16	(tmp_xor_data_16	),
				.tmp_xor_data_32	(tmp_xor_data_32	),
				.tmp_xor_data_64	(tmp_xor_data_64	),
				.iv_shift_1		(iv_shift_1		),
				.iv_shift_8		(iv_shift_8		),
				.iv_shift_16		(iv_shift_16		),
				.iv_shift_32		(iv_shift_32		),
				.iv_shift_64		(iv_shift_64		),
				.iv_back_tmp		(iv_back_tmp		),
				.buff_load		(buff_load		),
				.buff_load_low		(buff_load_low		),
				.iv_load		(iv_load		)
				//.sel_left		(sel_left		),
				//.sel_right		(sel_right		)
				);	


endmodule