ufpga2.v

USBRTL电路的VHDL和Verilog代码

module Ufpga2 (
	      clock48,
	      rcvin,   // usbrcv on lg schematic
	      vpin,
	      vmin,
	      vmo,
	      vpo,
	      usboen,
          usbclockout,
	      usbclock,
	      pwronreset,
	      usbreset,
	      endpwrdata,   // ep34wrdata
	      datapacketok,
	      datapacketnotok,
	      descriptorindex,
	      setupaddr,
	      setupdata,  // rom data on lg schematic
	      romoen,
  	      currentalternatesetting,
          //    endp0noncorecmd,

	      ep0wen,
	      endp0wrready,
	      ep0ren,
	      endp0rddata,
	      endp0rdready,

	      ep1ren,   // active low read enable
	      endp1rddata,
	      endp1rdready,

	     /* 
			  ep2ren,
	          endp2rddata,
	          endp2rdready,

	          ep3ren,
	          endp3rddata,
	          endp3rdready,
         */
		 
	      endp0internaltogglebit,
	      setupcycle,
	      setupbyteaddr,
	      setupdataout,
	      rcvack,
	      suspend
	      );



  input	       clock48;
  input	       rcvin;
  input	       vpin;
  input	       vmin;
  output       vmo;
  output       vpo;
  output       usboen;
  output       usbclockout;
  input	       usbclock;
  input	       pwronreset;
  output       usbreset;
  output [7:0] endpwrdata;
  output       datapacketok;
  output       datapacketnotok;  
  output [6:0] descriptorindex;
  output [7:0] setupaddr;
  input [7:0]  setupdata;
  output       romoen;
  output [7:0]  currentalternatesetting;
  output       ep0wen;
  input	       endp0wrready;
  output       ep0ren;
  input [7:0]  endp0rddata;
  input	       endp0rdready;
  output       ep1ren;
  input [7:0]  endp1rddata;
  input	       endp1rdready;

   /* 
	  output       ep2ren;
      input [7:0]  endp2rddata;
      input	       endp2rdready;
      output       ep3ren;
      input [7:0]  endp3rddata;
      input	       endp3rdready;
    */

 output       endp0internaltogglebit;
 output       setupcycle;
 input [2:0]  setupbyteaddr;
 output [7:0]  setupdataout;
 output       rcvack;
 output       suspend;
  
  
  wire [10:0] framenumber;	// doesn't go anywhere
  
  wire	       endp0rd,endp1rd,romen;
  wire		   endp0wr;

  wire	       ep0ren = ~endp0rd;
  wire	       ep0wen = ~endp0wr;
  wire	       ep1ren = ~endp1rd;
  /*   wire	       ep2ren = ~endp2rd;
       wire	       ep3ren = ~endp3rd;
  */
  wire	       romoen = ~romen;

  wire	       clock48;
Ucore usbcore (
        // inputs from bus
        .clock48 (clock48),
        .rcvin (rcvin),
        .vpin (vpin),
        .vmin (vmin),
 
        // outputs
        .vmo (vmo),
        .vpo (vpo),
        .usboen (usboen),

	// clock outputs
        .pwronreset(pwronreset),
	    .usbreset (usbreset),
        .usbclockout(usbclockout),
        .usbclock(usbclock),

	// outputs to endpoints
	.endpwrdata (endpwrdata),
	.datapacketok (datapacketok),
	.datapacketnotok (datapacketnotok),

       // rom
        .devromdescriptorindex(descriptorindex),
        .devromsetupaddr(setupaddr),
        .romdevsetupdata(setupdata),
        .romen(romen),
	.endp0internaltogglebit(endp0internaltogglebit),
        .setupcycle(setupcycle),
        .setupbyteaddr(setupbyteaddr),
        .setupdata(setupdataout),
	.rcvack(rcvack),
	.suspend(suspend),
	.framenumber(framenumber),

//	`include "Udevconnections.v"
// include file included inline here so port name connections
// could be changed if needed.
	.currentalternatesetting (currentalternatesetting),
	// connections to endpoint0
	//.endp0noncorecmd (endp0noncorecmd),
	.endp0wr (endp0wr),
	.endp0wrready (endp0wrready),
	.endp0wrstall (1'b0),
	.endp0rd (endp0rd),
	.endp0rddata (endp0rddata),
	.endp0rdready (endp0rdready),
    .endp0rdstall (1'b0),

	// connections to endpoint1 - read only
	.endp1rd (endp1rd),
	.endp1rddata (endp1rddata),
	.endp1rdready (endp1rdready),
	.endp1rdstall (1'b0)
   /*
       	// connections to endpoint2 - read only
	     .endp2rd (endp2rd),
	     .endp2rddata (endp2rddata),
	     .endp2rdready (endp2rdready),
	     .endp2rdstall (1'b0),

	    // connections to endpoint3 - read only
	     .endp3rd (endp3rd),
	     .endp3rddata (endp3rddata),
	     .endp3rdready (endp3rdready),
         .endp3rdstall (1'b0)
    */
	);

endmodule // fpga2