modulator.v

运用FPGA控制AD9957的操作

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:       xuwei
// 
// Create Date:    13:20:58 11/13/2007 
// Design Name: 
// Module Name:    modulator 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module modulator(gclk,// nrst, 
				ex_opt, ex_opt0,ex_opt1, ex_ppt,ex_pm, ex_pms, ex_bds, ex_clk,
				dout, io_update, io_reset, osk, tx_en, pdclk,rt,pwr_dwn,profile,
				sdio,sdo,ncs,sclk,tp,tp_out);
    input gclk;
//    input nrst;
    input ex_opt;
	input ex_opt0;
	input ex_opt1;
	input ex_ppt;
	input ex_pm;
	input ex_pms;
	input ex_bds;
	input ex_clk;
	input sdo;
	input [7:0] tp; 
	
    output [17:0] dout;
    output io_update;
    output io_reset;
    output osk;
    output tx_en;
    output pdclk;
	output [2:0] profile;
	output rt;
	output pwr_dwn;
	output sdio;
	output ncs;
	output sclk;
	output [5:0] tp_out;
	
	wire nrst;
//    reg [17:0] dout;
//    reg io_update;
//    reg io_reset;
//	reg [2:0] profile;

//    reg osk;
//    reg tx_en;
//    reg pdclk;
//	reg rt,pwr_dwn;	
	reg [5:0] tp_out;
	///////////////////////////////////////////////////////////////////////////////////////////
	reg start_single,start_dac,start_qudc;
	wire end_single; 
	wire [1:0] option;
	wire clk_locked;
	wire clk;
	assign nrst = clk_locked;
	assign dout = 17'b0;
	assign osk = 0;
	assign tx_en = 0;
	assign pdclk = 0;
	assign rt = 0;
	assign pwr_dwn = 0;
	assign osk = 0;
	///////////////////////////////////////////////////////////////////////////////////////////
	//
	parameter IDLE = "idle";
	parameter START = "start";
	parameter SINGLE_START = "s_str";
	parameter SINGLE_END = "s_end";
	parameter DAC_START = "d_str";
	parameter DAC_END = "d_end";
	parameter QUDC_START = "q_str";
	parameter QUDC_END = "q_end";
	parameter END = "end";

	
	///////////////////////////////////////////////////////////////////////////////////////////
	//
	//  main programme
	//
	///////////////////////////////////////////////////////////////////////////////////////////
	//
	//clok manage
	
	dcmclk clkdcm_inst(
            .CLKIN_IN(gclk),
            .CLKIN_IBUFG_OUT(),
            .CLK0_OUT(clk),              //100MHz Global Clock Output          
            .LOCKED_OUT(clk_locked)             //Clock is Locked When High
		  );
	/////////////////////////////////////////////////////////////////////////////////////////
	//single mode
	ad9957_single ad9957_single_inst (
		.clk(clk), 
		.nrst(nrst), 
		.start(start_single), 
		.ncs(ncs), 
		.sclk(sclk), 
		.sdio(sdio), 
		.sdo(sdo), 
		.io_update(io_update), 
		.io_reset(io_reset), 
		.profile(profile), 
		.end_single(end_single)
	);
	///////////////////////////////////////////////////////////////////////////////////////////
	// shaping filter
	
//	rcosflt_lookup rcosflt_lookup_inst (
//		.clk(clk), 
//		.nrst(nrst), 
//		.din(flt_din), 
//		.dout(flt_dout)
//	);
	///////////////////////////////////////////////////////////////////////////////////////////
	//test
	assign option = 2'b00;
	always@(posedge clk)
	begin
		if(!nrst)
			tp_out <= 6'b000000;
		else
		begin
			tp_out[5] <= 1'b1;
			tp_out[4] <= 1'b0;
			if(tp_out[3:0] == 4'b1111)
				tp_out[3:0] <= 4'b0000;
			else
				tp_out[3:0] <= tp_out[3:0] + 1;
		end 	
	end
	
	///////////////////////////////////////////////////////////////////////////////////////////
	//operating process
	reg[8*10:0] state_cur,state_nxt;
	reg [2:0] ex_opt0_sync;
	always@(posedge clk)
	begin
		if(!nrst)
			ex_opt0_sync <= 3'b000;
		else
			ex_opt0_sync <= {ex_opt0_sync[1:0],ex_opt0};
	end
	//fsm1
	always@(posedge clk)
	begin
		if(!nrst)
			state_cur <= IDLE;
		else
			state_cur <= state_nxt; 
	end
	//fsm2
	always@(nrst,state_cur,ex_opt0_sync,option,end_single)
	begin
		if(!nrst)
		begin
			state_nxt <= IDLE;
		end
		else
		begin
			case(state_cur)
				IDLE:
				begin
					if(ex_opt0_sync[2] == 1'b1)
						state_nxt <= START;
					else
						state_nxt <= START;
				end
				START:
				begin
					case(option)
					2'b00:
						state_nxt <= SINGLE_START;
					2'b01:
						state_nxt <= DAC_START;
					2'b10:
						state_nxt <= QUDC_START;
					default:
						state_nxt <= IDLE;
					endcase
				end
				SINGLE_START:
				begin
					state_nxt <= SINGLE_END;
				end
				SINGLE_END:
				begin
					if(end_single == 1)
						state_nxt <= END;
					else
						state_nxt <= SINGLE_END;
				end
				DAC_START:
				begin
					state_nxt <= DAC_END;
				end
				DAC_END:
				begin
					if(end_single == 1)
						state_nxt <= END;
					else
						state_nxt <= DAC_END;
				end
				QUDC_START:
				begin
					state_nxt <= QUDC_END;
				end
				QUDC_END:
				begin
					if(end_single == 1)
						state_nxt <= END;
					else
						state_nxt <= QUDC_END;
				end
				END:
					state_nxt <= END;
				default:
				begin
					state_nxt <= IDLE;
				end
			endcase
		end
	end
	//
	always@(posedge clk)
	begin
		if(!nrst)
		begin
			start_single <= 1'b0;
			start_dac <= 1'b0;
			start_qudc <= 1'b0;
		end
		else
		begin
			case(state_cur)
				IDLE:
				begin
					start_single <= 1'b0;
					start_dac <= 1'b0;
					start_qudc <= 1'b0;
				end
				START:
				begin
					start_single <= 1'b0;
					start_dac <= 1'b0;
					start_qudc <= 1'b0;
				end
				SINGLE_START:
				begin
					start_single <= 1'b1;
				end
				SINGLE_END:
				begin
					if(end_single == 1)
						start_single <= 1'b0;
				end
				DAC_START:
				begin
					start_dac <= 1'b1;
				end
				DAC_END:
				begin
					if(end_single == 1)
						start_dac <= 1'b0;
				end
				QUDC_START:
				begin
					start_qudc <= 1'b1;
				end
				QUDC_END:
				begin
					if(end_single == 1)
						start_qudc <= 1'b0;
				end
				default:
				begin
					start_single <= 1'b0;
					start_dac <= 1'b0;
					start_qudc <= 1'b0;
				end
			endcase
		end
	end
	////////////////////////////////////////////////////////////////////////////////
	//
endmodule