serial.v

运用FPGA控制AD9957的操作

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:15:21 11/13/2007 
// Design Name: 
// Module Name:    serial 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module serial(clk, nrst, start, len_reg, addr, din, ncs, sclk, ser_in, ser_out, sd_io, dout,end_serial);
    input clk;
    input nrst;
	input start;
	input [6:0] len_reg;
    input [7:0] addr;
    input [63:0] din;
	input ser_in;
	
    output ncs;
    output sclk;
	output sd_io;
  
    output ser_out;
	output [63:0] dout;
	output end_serial;
	
	////////////////////////////////////////////////////////////////////////
	reg ncs;
    reg sclk;
//    reg sdio;
	reg [63:0] dout/*synthesize syn_preserve = 1*/;
	reg end_serial;
	reg ser_out;
	reg sd_io;
	////////////////////////////////////////////////////////////////////////////
	//local varible
//	wire start_rd,start_wr;
	reg g_addr_data;
	reg [63:0] shift_data;
	reg [7:0] shift_cnt;
	reg [30:0] state_cur,state_next;
	parameter 	STATE_IDLE = "s0",
				STATE1 = "s1",
				STATE2 = "s2",
				STATE3 = "s3",
				STATE4 = "s4",
				STATE5 = "s5",
				STATE6 = "s6",
				STATE7 = "s7",
				STATE8 = "s8",
				STATE9 = "s9",
				STATE10 = "s10",
				STATE11 = "end";

	reg[1:0] dly_cnt;
	///////////////////////////////////////////////////////////////////////////
	//assign
	///////////////////////////////////////////////////////////////////////////
	//
//	assign start_rd = (start == 1)&&(addr[7] == 1)? 1'b1:1'b0;
//	assign start_wr = (start == 1)&&(addr[7] == 0)? 1'b1:1'b0;
	//////////////////////////////////////////////////////////////////////////
	//fsm
	always@(posedge clk,negedge nrst)
	begin
		if(!nrst)
			state_cur <= STATE_IDLE;
		else
			state_cur <= state_next;
	end
	////////////////////////////////
	//
	always@*//(nrst,state_cur,shift_cnt,start,dly_cnt)
	begin
		if(!nrst)
			state_next = STATE_IDLE;
		else
		begin
			case(state_cur)
				STATE_IDLE:
				begin
					if(start == 1)
						state_next = STATE1;
					else
						state_next = STATE_IDLE;
				end
				/////////////////////////write addr/data to serial interface
				STATE1:
				begin
						state_next = STATE2;
				end
				STATE2:							//delay 4 clk period
				begin
					if(dly_cnt == 3)
						state_next = STATE3;
					else
						state_next = STATE2;
				end
				STATE3:                      	//delay 4 clk period
				begin
					if(dly_cnt == 3)
						state_next = STATE4;
					else
						state_next = STATE3;
				end
				STATE4:
				begin
					if(shift_cnt == 0)			// end to write 
						state_next = STATE5;
					else						// continue to write
						state_next = STATE1;
				end
				STATE5:
				begin
					if(g_addr_data == 0)      	//start to write/read data
						state_next = STATE6;
					else						//end to write data
						state_next = STATE11;
				end
				STATE6:
				begin
					if(addr[7] == 0)      		//wr
						state_next = STATE1;
					else						//rd
						state_next = STATE7;
				end
				/////////////////////////read data from serial interface
				STATE7:
				begin
					state_next = STATE8;
				end
				STATE8:							//delay 4 clk period
				begin
					if(dly_cnt == 3)
						state_next = STATE9;
					else
						state_next = STATE8;
				end
				STATE9:							//delay 4 clk period
				begin
					if(dly_cnt == 3)
						state_next = STATE10;
					else
						state_next = STATE9;
				end
				STATE10:
				begin
					if(shift_cnt != 0)           //continue to read data
						state_next = STATE7;
					else                         //end to read data
						state_next = STATE11;
				end
				STATE11:
				begin
					state_next = STATE_IDLE;
				end
				default:
				begin
					state_next = STATE_IDLE;
				end
			endcase
		end
	end
	////////////////////////////////////////////////
	//fsm3
	always@(posedge clk)
	begin
		if(!nrst)
			init;		
		else
		begin
			case(state_cur)
				STATE_IDLE:
				begin
					init;
				end
				STATE1:
				begin
					ncs <= 1'b0;
					ser_out <= shift_data[shift_cnt];
					sclk <= 1'b0;
				end
				STATE2:
				begin
					if(dly_cnt == 3)
						dly_cnt <= 0;
					else
						dly_cnt <= dly_cnt + 1;
				end
				STATE3:
				begin
					sclk <= 1'b1;
					if(dly_cnt == 3)
						dly_cnt <= 0;
					else
						dly_cnt <= dly_cnt + 1;
				end
				STATE4:
				begin
					sclk <= 1'b1;
					if(shift_cnt != 0)
						shift_cnt <= shift_cnt - 1;
				end
				STATE5:
				begin
					shift_cnt <= len_reg -1;
					shift_data <= din;
				end
				STATE6:
				begin
					g_addr_data <= 1'b1;
					ncs <= 1'b1;
				end
				/////////////////////////read data from serial interface
				STATE7:
				begin
//					shift_cnt <= len_reg -1;
					sd_io <= 1;
					ncs <= 1'b0;
					sclk <= 1'b0;
				end
				STATE8:							//delay 4 clk period
				begin
					if(dly_cnt == 3)
						dly_cnt <= 0;
					else
						dly_cnt <= dly_cnt + 1;
				end
				STATE9:							//delay 4 clk period
				begin
					sclk <= 1'b1;
					if(dly_cnt == 3)
						dly_cnt <= 0;
					else
						dly_cnt <= dly_cnt + 1;
				end
				STATE10:
				begin
					dout[shift_cnt] <= ser_in;
					if(shift_cnt != 0)
						shift_cnt <= shift_cnt - 1;
				end
				STATE11:
				begin
					end_serial <= 1'b1;
				end
				default:
				begin
				end
			endcase
		end
	end
	/////////////////////////////////////////
	task init;
	begin
		ncs <= 1'b1;
		ser_out <= 1'b0;
		sclk <= 1'b0;
//		io_reset <= 1'b0;
//		io_update <= 1'b0;
		end_serial <= 1'b0;
		dout <= 64'h00000000;
		shift_data <= addr;
		shift_cnt <= 7;
		g_addr_data <= 1'b0;
		dly_cnt <= 0;
		sd_io <= 0;
	end
	endtask
endmodule