alu.v

verilog语言写的8位CPU源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    22:07:18 11/07/07
// Design Name:    ALU.v
// Module Name:    ALU
// Project Name:   KD-CPU
// Target Device:  FPGA
// Tool versions:  
// Description:	 ALU for KD-CPU
//	PS:             doen by myself
// Dependencies:
// Author:        zhengzhong
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ALU(ALU_O,ALU_C,C_in,op,AC_in,GR_in);
  

  parameter width=8;
  output ALU_C;                          //For C flags
  output[width-1:0] ALU_O;               //The result of CPU 
  input C_in;                            //C flags in
  input[4:0] op;                         //Operation code
  input[width-1:0] AC_in;					           //AC 
  input[width-1:0] GR_in;                //GR
  reg[width-1:0] ALU_O;						  
  reg ALU_C; 

  always@(C_in or op or AC_in or GR_in)
        begin
		  case(op)
		  5'b00010:begin{ALU_C,ALU_O}={C_in,AC_in};end        //->AC
		  5'b00011:begin{ALU_C,ALU_O}={C_in,GR_in};end        //->GR
		  5'b00100:begin{ALU_C,ALU_O}=AC_in+GR_in;end         //加法
		  5'b00101:begin{ALU_C,ALU_O}=AC_in-GR_in;end        	//减法
		  5'b00110:begin{ALU_C,ALU_O}=AC_in+GR_in+C_in;end    //带进位加法
		  5'b00111:begin{ALU_C,ALU_O}=AC_in-GR_in-C_in;end    //带借位减法
		  5'b01000:begin{ALU_C,ALU_O}={C_in,AC_in&GR_in};end  //按位与,进位不变
		  5'b01001:begin{ALU_C,ALU_O}={C_in,AC_in^GR_in};end  //按位异或,进位不变
		  5'b01010:begin{ALU_O,ALU_C}={C_in,GR_in};end        //带进(借)位循环左移一位
		  5'b01011:begin{ALU_C,ALU_O}={GR_in,C_in};end        //带进(借)位循环右移一位
		  default: begin{ALU_C,ALU_O}={C_in,8'b0};end

		  endcase
		  end

endmodule