poppushtestbch.v

verilog语言写的8位CPU源代码

`timescale 1ns/10ps
module POPPuSHTestbch;
    wire[7:0] data;
    wire [7:0] address_out;
    wire CS;
    wire READ;
    wire WRITE;
    reg clk;
    reg reset;
    
    KD_CPU b(.data(data),.address_out(address_out),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset));
    memory m(.mem_data(data),.mem_address(address_out),.CS(CS),.WRITE(WRITE),.READ(READ));
             
    initial
    begin  
    clk = 'b0;
    reset = 'b0;
    
    m.mem[0]='b0;           //mov mi -> AC
    m.mem[1]=30;            //Adress is 20     
    m.mem[2]='b10110000;    //push AC
    
    m.mem[3]='b0;           //mov mi -> AC
    m.mem[4]=31;            //Adress is 21      
    m.mem[5]='b00010001;    //mov AC to R1
     
    m.mem[6]='b10111000;    //pop AC
    
    m.mem[7]='b00100001;    //AC+GR->AC
    m.mem[8]='b00001000;    //mov ac to mem
    m.mem[9]='h40;          //mem address is 'h40
    
    
    m.mem[10]='b0;          //mov mi ->AC
    m.mem[11]=32;           //address is 22
    m.mem[12]='b00111001;   //AC-GR-C;
        
    m.mem[13]='b00001000;    //mov ac to mem
    m.mem[14]='h41;          //mem address is 'h41
    
    m.mem[15]='b0;          //mov mi ->AC
    m.mem[16]=33;           //address is 23
    
    m.mem[17]='b01000001;   //xor AC GR
    m.mem[18]='b00001000;    //mov ac to mem
    m.mem[19]='h42;          //mem address is 'h42
    
    m.mem[20]='b01011001;   //SHCL AC,GR
    m.mem[21]='b00001000;    //mov ac to mem
    m.mem[22]='h43;          //mem address is 'h43
    
    m.mem[23]='b01010001;   //SHCR AC,GR
    m.mem[24]='b00001000;    //mov ac to mem
    m.mem[25]='h44;          //mem address is 'h44
    
    m.mem[26]='b11111000;//HALT
       
    m.mem[30]='hE1;
    m.mem[31]='h43;   //01000011
    m.mem[32]='h51;
    m.mem[33]='hF1;   //11110001
    //m.mem['h40]='hE1+'h43;
    //m.mem['h41]='h51-'h43-C;
    //m.mem['h42]='hF1^'h43;
    //m.mem['h43]=SHCL 'h43;
    //m.mem['h44]=SHCR 'h43;
   #1 reset=1;
   #5000 $display( "Result is:%h.\n",m.mem[40]);
   # 5000 $stop;
   end

   always #100 clk=~clk;
 endmodule