ibelieve.v

<I believe> song _verilog code for any device.

module Ibelieve(sys_clk,rst_n,sp);
	input			sys_clk,rst_n;
	output		sp;
	
	reg 			sp;
	reg[3	:0]	high,med,low;
	reg[13:0]	divider,origin;
	reg[7	:0]	counter;
	reg[23:0] clk_cnt;
 
  always @ (posedge sys_clk or negedge rst_n)
    if (!rst_n)
        clk_cnt <= 24'd0;
    else
        clk_cnt <= clk_cnt + 1'b1;

 wire  clk_6mhz = clk_cnt[2];
 wire  clk_4hz  = clk_cnt[23];
 wire carry=(divider==16383);

	always @(posedge clk_6mhz)
		begin  
			if(carry)
				divider=origin;
      else     
      	divider=divider+1'b1;
		end

	always@(posedge carry)
  	begin
     	sp =~sp;
  	end
  
  
  always@(posedge clk_4hz)
   begin
     case({high ,med ,low})
     	12'b000000000011:	origin=14'd7281;
     	12'b000000000101:	origin=14'd8730;
     	12'b000000000110:	origin=14'd9565;
     	12'b000000000111:	origin=14'd10310;
     	12'b000000010000:	origin=14'd10647;
     	12'b000000100000:	origin=14'd11272;
     	12'b000000110000:	origin=14'd11831;
     	12'b000001010000:	origin=14'd12556;
     	12'b000001100000:	origin=14'd12974;
     	12'b000100000000:	origin=14'd13516;
     	12'b000000000000:	origin=14'd16383;
		default:origin=14'd0;
     endcase
  end

  always@(posedge clk_4hz)
		begin
			if(counter==8'd50)      
    		counter=8'd0;
      else  
       	counter=counter+1'b1;
      case(counter)             
      8'd 0:{high,med,low}=12'b0000_0101_0000; 
 			8'd 1:{high,med,low}=12'b0000_0101_0000; 
 			8'd 2:{high,med,low}=12'b0000_0001_0000;   
 			8'd 3:{high,med,low}=12'b0000_0010_0000;
 			8'd 4:{high,med,low}=12'b0000_0010_0000;
 			8'd 5:{high,med,low}=12'b0000_0000_0000;
 			8'd 6:{high,med,low}=12'b0000_0010_0000;
 			8'd 7:{high,med,low}=12'b0000_0011_0000;
 			8'd 8:{high,med,low}=12'b0000_0100_0000;
 			8'd 9:{high,med,low}=12'b0000_0100_0000;
 			8'd10:{high,med,low}=12'b0000_0011_0000;
 			8'd11:{high,med,low}=12'b0000_0100_0000;
 			8'd12:{high,med,low}=12'b0000_0100_0000;
 			8'd13:{high,med,low}=12'b0000_0101_0000;
 			8'd14:{high,med,low}=12'b0000_0101_0000;
 			8'd15:{high,med,low}=12'b0000_0011_0000;  			 
 			8'd16:{high,med,low}=12'b0000_0011_0000; 
 			8'd17:{high,med,low}=12'b0000_0011_0000;   
 			8'd18:{high,med,low}=12'b0000_0011_0000;
 			8'd19:{high,med,low}=12'b0000_0000_0000;
 			8'd20:{high,med,low}=12'b0000_0000_0000;
 			8'd21:{high,med,low}=12'b0000_0000_0000;
 			8'd22:{high,med,low}=12'b0000_0000_0000;
 			8'd23:{high,med,low}=12'b0000_0011_0000;
 			8'd24:{high,med,low}=12'b0000_0011_0000;
 			8'd25:{high,med,low}=12'b0000_0000_0110;
 			8'd26:{high,med,low}=12'b0000_0010_0000;
 			8'd27:{high,med,low}=12'b0000_0010_0000;
 			8'd28:{high,med,low}=12'b0000_0010_0000;
 			8'd29:{high,med,low}=12'b0000_0000_0000;
 			8'd30:{high,med,low}=12'b0000_0000_0000;     
 			8'd31:{high,med,low}=12'b0000_0000_0110; 			
 			8'd32:{high,med,low}=12'b0000_0000_0111;   
 			8'd33:{high,med,low}=12'b0000_0001_0000;
 			8'd34:{high,med,low}=12'b0000_0001_0000;
 			8'd35:{high,med,low}=12'b0000_0000_0111;
 			8'd36:{high,med,low}=12'b0000_0001_0000;
 			8'd37:{high,med,low}=12'b0000_0001_0000;
 			8'd38:{high,med,low}=12'b0000_0010_0000;
 			8'd39:{high,med,low}=12'b0000_0010_0000;
 			8'd40:{high,med,low}=12'b0000_0010_0000;
 			8'd41:{high,med,low}=12'b0000_0010_0000;
 			8'd42:{high,med,low}=12'b0000_0010_0000;
 			8'd43:{high,med,low}=12'b0000_0000_0000;
 			8'd44:{high,med,low}=12'b0000_0000_0000;
 			8'd45:{high,med,low}=12'b0000_0000_0000;
 			8'd46:{high,med,low}=12'b0000_0000_0000;
 			8'd47:{high,med,low}=12'b0000_0000_0000;
 			default:{high,med,low}=12'd0;
   endcase//后边乐曲片断此处省略 
end
endmodule