代码搜索结果
找到约 10,000 项符合
V 的代码
mult.v
module mult(outcome,a,b);
parameter size=8;
input[size:1] a,b;
output[2*size:1] outcome;
assign outcome=a*b;
endmodule
aoi.v
module AOI(A,B,C,D,F);
input A,B,C,D;
output F;
wire A,B,C,D,F;
assign F= ~((A&B)|(C&D));
endmodule
clktest.v
module clockadjuster(clkin,clkout,test_item,delay_enable,output_select);
input clkin;
output clkout;
input [1:0] test_item; //00-- test function disable
rcvr.v
/******************************************************************************
*
* File Name: rcvr.v
* Version: 1.1
* Date: January 22, 2000
* Model: Receiver Chip
*
*
uart.v
/******************************************************************************
*
* File Name: uart.v
* Version: 1.1
* Date: January 22, 2000
* Model: Uart Chip
* Depe
uart_if.v
`timescale 1 ns / 1 ns
module uart_if(clk,rst_n,txd,rxd,data_out,data_in);
input clk,rst_n,rxd;
input[7:0] data_in;
output txd;
output[7:0] data_out;
reg [7:0] data_out;
reg [7
txmit.v
/******************************************************************************
*
* File Name: txmit.v
* Version: 1.1
* Date: January 22, 2000
* Model: Uart Chip
*
*
**
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
receiver.v
module receiver(
rst,
qd,
clk,
r_ram_wdb,
r_ram_wab,
r_ram_wen,
r_req,
start_read
// interrupt
);
/*** ports ***/
input rst;
input qd;
input clk;
output r_ram_wdb;