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V 的代码
datacnt.v
module datacnt(
clk,
rst,
r_ram_rdb,
r_ram_rab,
r_req,
s_ram_wdb,
fifo_wen,
cmd,
cmdack,
addr,
datain,
dataout,
start_read,
interru
lcdmodule.v
module LCDmodule(clk, RxD, LCD_RS, LCD_RW, LCD_E, LCD_DataBus);
input clk, RxD;
output LCD_RS, LCD_RW, LCD_E;
output [7:0] LCD_DataBus;
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver
test.v
module test(SW,LCD_XX);
input [4:0]SW;
output [4:0]LCD_XX;
reg [4:0]LCD_XX;
always @(SW)
begin
case(SW)
5'b00000:LCD_XX=5'b00001;
5'b00010:LCD_XX=5'b00010;
5'b
lcdfinal.v
//`include "F:\jeffie\quartus\lcdfinal\lcdfinal.v"
//`include "F:\jeffie\quartus\lcdfinal\LCD_TEST.v"
//`include "F:\jeffie\quartus\lcdfinal\Reset_Delay.v"
module lcdfinal
(
////////////////
choose.v
module choose(cho,LCD_XX);
input [2:0]cho;
output [2:0]LCD_XX;
reg [4:0]LCD_XX;
always @(cho)
begin
case(cho)
3'b000:LCD_XX=5'b00001;
3'b001:LC
tester.v
// hds_header_start
//
// Module UART_TXT.tester.rtl
//
// Created:
// by - user.group (host.domain)
// at - 19:23:16 28 Aug 2001
//
// Generated by Mentor Graphics' HDL Desi
command.v
module command(
CLK,
RESET_N,
SADDR,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
REF_REQ,
INIT_REQ,
params.v
// Address Space Parameters
`define ROWSTART 8
`define ROWSIZE 12
`define COLSTART 0
`define COLSIZE 8
`define BANKSTART 20
`define BANKSIZE
stack.v
/*****************************************/
/** 8bit RISC MCU desing **/
/** stack module **/
/** BY yuzhijie **/
/** 2006.10.2
ir.v
/*****************************************/
/** 8bit RISC MCU desing **/
/** ir module **/
/** BY yuzhijie **/
/** 2006.10.2