代码搜索结果
找到约 10,000 项符合
V 的代码
protocol.v
module protocol(
clk,
rst,
p_headadd,
p_length,
p_rd,
p_empty,
p_data,
udp.v
module udp(
clk,
rst,
data_i,
addr,
info_en,
length,
headadd,
des_ip,
sou_ip,
des_port,
sou_port,
send_udp,
udp_over,
udp_ing,
receive.v
module receive(
clk,
rst,
add,
dataout,
/******/
empty,
indx,
index
ram.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
gigatran.v
module gigatran(
clk125,
rst,
/******/
mode,
crs,
col,
txd,
tx_en,
tx_er,
gtx_clk,
lan_rst,
/********/
data.v
module data(
rxc,
rst,
/******/
rx_en,
rx_er,
rxd,
/******/
dataout,
ena,
content.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
crc.v
module crc(
rst,
clk,
din, //input data
vin, //input data valid flag
dout, //output data
vout //output data valid flag
);
input rst;
input clk;
input[7:0] din;
input vin
system.v
/////////////////////////////////////////////////////////////////////////
// Module system.v
// Hierarchy: None ( It is the master )
// Module function:
// Module system.v generates input signals fo
controller.v
////////////////////////////////////////////////////////////////////////////
// Module controller.v
// Hierarchy: chip_core.v
// Module function:
// Module controller.v provides several functions: