receive.v

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

module receive(
               clk,		   
               rst,
               add,
               dataout,
               /******/
               empty,
               indx,
               index_en,
               /******/
               rxc,
               rx_dv,
               rx_er,
               rxd,
		   souadd,	  //modified orignal there is no souadd
               error
               );
    input clk;
    input rst; 
    input[12:0] add;  
    output [7:0] dataout;
    output empty;
    output [15:0] indx;
    input index_en;
    input rxc;
    input rx_dv;
    input rx_er;
    input [7:0] rxd;
    input [47:0] souadd;
    output error;
    
    wire[15:0] info;
    wire latch;
    wire full;
    wire[12:0] addr;
    wire[7:0] data;
    wire ena;
    wire[7:0] rxdata;
    wire rxempty;
    wire rxfull;
    wire rxclk;

BUFG B1    (
		.I(rxc),
		.O(rxclk)
		) ;


content    uu0 (
              .din(info),
		  .wr_en(latch),
		  .wr_clk(rxclk),
		  .rd_en(index_en),
		  .rd_clk(clk),
		  .ainit(1'b0),
		  .dout(indx),
		  .full(full),
		  .empty(empty)
		  );

packet_cache uu1 (
                  .addra(addr),
                  .addrb(add),
                  .clka(rxclk),
                  .clkb(clk),
                  .dina(data),
                  .doutb(dataout),
                  .wea(ena)
                  );
                  
data    uu2(
            .rxc(rxclk),
            .rst(rst),
            /******/
            .rx_en(~rxempty),
            .rx_er(rxfull),
            .rxd(rxdata),
            /******/
            .dataout(data),
            .ena(ena),
            .error(error),
            .headadd(info[15:11]),
            .addr(addr),
            .length(info[10:0]),
            .latch(latch),
            .full(full),
		/******/
		.souadd(souadd)
            );

rxdcache uu3 (
		.din(rxd),
		.wr_en(rx_dv),
		.wr_clk(rxc),
		.rd_en(~rxempty),
		.rd_clk(rxclk),
		.ainit(1'b0),
		.dout(rxdata),
		.full(rxfull),
		.empty(rxempty)
		);   

endmodule