data.v

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

module data(
            rxc,
            rst,
            /******/
            rx_en,
            rx_er,
            rxd,
            /******/
            dataout,
            ena,
            error,
            headadd,
            addr,
            length,
            latch,
            full,
            /********/
            souadd
            );
    input rxc;
    input rst;
    input rx_en;
    input rx_er;
    input [7:0] rxd;
    output[7:0] dataout;
    reg[7:0] dataout;
    output ena;
    reg ena;
    output error;
    output [4:0] headadd;
    reg[4:0] headadd;
    output [12:0] addr;
    reg[12:0] addr;	   //modified the reg[12:0] addr orignal is reg[15:0]
    output [10:0] length;
    output latch;
    reg latch;
    input full;
    input[47:0] souadd;
    
    reg[6:0] current;
    reg[6:0] next;
    
    reg[3:0] counter;
    
    reg[31:0] crc;
    reg[31:0] cache;
    wire[31:0] crc2;
    wire[7:0] cc;

    reg rx_dv;

    reg abandon;
    reg[47:0] mac_add;
    
    parameter IDLE=7'h01, PRE=7'h02,DELIM=7'h04,
              REC=7'h08, CRC=7'h10, ERROR=7'h20,
              CACHE=7'h40;
              
         
assign length=addr[7:0]+1; //modified, orignal is addr[10:0]
assign error=current[5];

assign cc=cache[31:24]; 
assign crc2={cache[24],cache[25],cache[26],cache[27],cache[28],cache[29],cache[30],cache[31],
             cache[16],cache[17],cache[18],cache[19],cache[20],cache[21],cache[22],cache[23],
             cache[8],cache[9],cache[10],cache[11],cache[12],cache[13],cache[14],cache[15],
             cache[0],cache[1],cache[2],cache[3],cache[4],cache[5],cache[6],cache[7]}^32'hffff_ffff;

always@(current or rxd or rx_dv or  full or abandon or counter or crc or crc2)
begin
	next=7'bxxxx_xxx;
    	case(current)
    	IDLE: begin
    		if(rx_dv&&!full)
    		next=PRE;
    		else if(rx_dv&&full)
    		next=ERROR;
    		else
    		next=IDLE;
    	end
    	PRE: begin
    		if(rxd==8'hd5)
    		next=DELIM;
    		else if(counter==9)
    		next=ERROR;
    		else
    		next=PRE;
    	end
    	DELIM: next=CACHE;    	
    	CACHE: begin
    		if(counter==4)
    		next=REC;
    		else
    		next=CACHE;
    	end
    	REC: begin
    		if(!rx_dv)
    		next=CRC;
    		else if(abandon)
    		next=ERROR;
    		else
    		next=REC;
    	end
    	CRC: begin    		
		if(crc==crc2)
    		next=IDLE;
    		else
    		next=ERROR;
    	
	end
    	ERROR: begin
    		if(!rx_dv)
    		next=IDLE;
    		else
    		next=ERROR;
    	end
	default: next=ERROR;
	endcase
end

always@(posedge rxc or negedge rst)
begin
	if(!rst) current<=IDLE;
	else current<=next;
end

always@(posedge rxc or negedge rst)
begin
	if(!rst) rx_dv<=1'b0;
	else rx_dv<=rx_en;
end
/**********generate the counter*********/
always@(posedge rxc or negedge rst)
begin
	if(!rst) begin
		counter<=4'h0;
	end
	else begin
		case(next)
		PRE: begin
			counter<=counter+1;
		end
		CACHE: begin
			counter<=counter+1;
		end
		default:
		counter<=4'h0;
		endcase
	end
end
/*******************the mac_add******************/
always@(posedge rxc or negedge rst)
begin
      if(!rst) mac_add<=48'h0000_0000;
	else begin
	     if(next==REC&&length<6)
	     mac_add<={mac_add[39:0],cache[31:24]};
      end
end
/*******************the bandon signal*****************/
always@(posedge rxc or negedge rst)
begin
	if(!rst) abandon<=1'b0;
	else begin
		case(next)
		REC: begin 
			if(rx_er)
			abandon<=1'b1;
			else if((length>7)&&(mac_add!=souadd)&&(mac_add!=48'hffff_ffff_ffff))
			abandon<=1'b1; 
			else 
			abandon<=1'b0;
		end
		default: abandon<=1'b0;
		endcase
	end
end
		     
/*****************generate the latch*******************/
always@(posedge rxc or negedge rst)
begin
	if(!rst) latch<=1'b0;
	else begin
		if(next==CRC&&crc==crc2)
		latch<=1'b1;
		else
		latch<=1'b0;
	end
end
/***********the ram operation*********/
always@(posedge rxc or negedge rst)
begin
	if(!rst) begin
		headadd<=5'h00;
		addr<=13'h0000;	//modified orignal is 16'h0000
		ena<=1'b0;
		dataout<=8'h00;
	end
	else begin
		if(latch==1'b1)
		headadd<=headadd+1;
		
		case(next)
		CACHE: begin
		//	addr<={headadd-1,8'h7ff};
			ena<=1'b0;			
		end
		REC: begin
		      if(counter==4)
			addr<={headadd,8'h00};	 //modified
			else
			addr<=addr+1;
			ena<=1'b1;
			dataout<=cache[31:24];
		end
		CRC: begin
			ena<=1'b0;
		end
		default: begin
			ena<=1'b0;
			addr<=13'h0000;
			dataout<=8'h00;
		end
	        endcase
	end
end
/******************the cache operation***********/
always@(posedge rxc or negedge rst)
begin
	if(!rst) cache<=32'h0000_0000;
	else begin
		case(next)
		REC,
		CACHE: begin
			cache<={cache[23:0],rxd};
		end
		CRC: begin
		end
		default: cache<=32'h0000_0000;
	        endcase
	end
end
/***************the CRC ***********/
	
always@(posedge rxc or negedge rst)
begin
	if(!rst) crc<=32'hffff_ffff;
	else begin
		case(next)
		REC: begin
			crc[0] <= crc[30] ^ cc[7] ^ crc[24] ^ cc[1];
			crc[1] <= crc[30] ^ crc[31] ^ cc[6] ^ cc[7] ^ crc[24] ^ cc[0] ^ crc[25] ^ cc[1];
			crc[2] <= crc[30] ^ crc[31] ^ cc[5] ^ cc[6] ^ cc[7] ^ crc[24] ^ crc[25] ^ crc[26] ^ cc[0] ^ cc[1];
			crc[3] <= cc[4] ^ crc[31] ^ cc[5] ^ cc[6] ^ crc[25] ^ crc[26] ^ crc[27] ^ cc[0];
			crc[4] <= crc[30] ^ cc[4] ^ cc[5] ^ cc[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[28] ^ cc[1] ^ cc[3];
			crc[5] <= crc[30] ^ cc[4] ^ crc[31] ^ cc[6] ^ cc[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[29] ^ cc[0] ^ cc[1] ^ cc[2] ^ cc[3]; 
			crc[6] <= crc[30] ^ crc[31] ^ cc[5] ^ cc[6] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ cc[0] ^ cc[1] ^ cc[2] ^ cc[3]; 
			crc[7] <= cc[4] ^ cc[5] ^ crc[31] ^ cc[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ cc[0] ^ cc[2]; 
			crc[8] <= cc[4] ^ cc[6] ^ cc[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[0] ^ cc[3];
			crc[9] <= cc[5] ^ cc[6] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ cc[2] ^ crc[1] ^ cc[3];
			crc[10] <= cc[4] ^ cc[5] ^ cc[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ cc[2] ^ crc[2];
			crc[11] <= cc[4] ^ crc[3] ^ cc[6] ^ cc[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ cc[3]; 
			crc[12] <= crc[30] ^ cc[5] ^ crc[4] ^ cc[6] ^ cc[7] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ cc[1] ^ cc[2] ^ cc[3]; 
			crc[13] <= cc[4] ^ crc[30] ^ crc[31] ^ cc[5] ^ cc[6] ^ crc[5] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[29] ^ cc[0] ^ cc[1] ^ cc[2];
			crc[14] <= cc[4] ^ crc[30] ^ cc[5] ^ crc[31] ^ crc[6] ^ crc[26] ^ crc[27] ^ crc[28] ^ cc[0] ^ cc[1] ^ cc[3]; 
			crc[15] <= cc[4] ^ crc[31] ^ crc[7] ^ crc[27] ^ crc[28] ^ crc[29] ^ cc[0] ^ cc[2] ^ cc[3]; 
			crc[16] <= cc[7] ^ crc[24] ^ crc[8] ^ crc[28] ^ crc[29] ^ cc[2] ^ cc[3];
			crc[17] <= crc[30] ^ cc[6] ^ crc[25] ^ crc[9] ^ crc[29] ^ cc[1] ^ cc[2];
			crc[18] <= crc[30] ^ cc[5] ^ crc[31] ^ crc[26] ^ cc[0] ^ cc[1] ^ crc[10];
			crc[19] <= cc[4] ^ crc[31] ^ crc[27] ^ cc[0] ^ crc[11];
			crc[20] <= crc[12] ^ crc[28] ^ cc[3]; 
			crc[21] <= crc[13] ^ crc[29] ^ cc[2];
			crc[22] <= crc[14] ^ cc[7] ^ crc[24];
			crc[23] <= crc[30] ^ cc[6] ^ cc[7] ^ crc[24] ^ crc[15] ^ crc[25] ^ cc[1];
			crc[24] <= crc[31] ^ cc[5] ^ cc[6] ^ crc[25] ^ crc[16] ^ crc[26] ^ cc[0];
			crc[25] <= cc[4] ^ cc[5] ^ crc[26] ^ crc[17] ^ crc[27];
			crc[26] <= crc[30] ^ cc[4] ^ cc[7] ^ crc[24] ^ crc[27] ^ crc[18] ^ crc[28] ^ cc[1] ^ cc[3];
			crc[27] <= crc[31] ^ cc[6] ^ crc[25] ^ crc[28] ^ crc[19] ^ crc[29] ^ cc[0] ^ cc[2] ^ cc[3];
			crc[28] <= crc[30] ^ cc[5] ^ crc[26] ^ crc[29] ^ cc[1] ^ cc[2] ^ crc[20];
			crc[29] <= cc[4] ^ crc[30] ^ crc[21] ^ crc[31] ^ crc[27] ^ cc[0] ^ cc[1]; 
			crc[30] <= crc[31] ^ crc[22] ^ crc[28] ^ cc[0] ^ cc[3]; 
			crc[31] <= crc[23] ^ crc[29] ^ cc[2];
		end
		CRC: begin
		end
		default: crc<=32'hffff_ffff;
	        endcase
	end
end 
endmodule