gigatran.v

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

module gigatran(
           clk125,	     
	     rst,
	     /******/
	     mode,
	     crs,
	     col,
	     txd,
	     tx_en,
	     tx_er,
	     gtx_clk,
	     lan_rst,
	     /********/
	     udp_data,
	     udp_headadd,
	     udp_addr,
	     udp_length,
	     udp_rd,
	     udp_empty,
	     udp_over,
	     /******/ 
	     s_des_ip,
	     s_sou_ip,
	     s_des_port,
	     s_sou_port,
	     s_sou_add,
	     a_des_ip,
	     a_des_add,
	     r_des_ip,
	     r_des_add,
	     r_empty,
	     r_rd
	     /********/
	     );
    input clk125;

    input rst;
    input mode;
    input crs;
    input col;
    output [7:0] txd;
    output tx_en;
    output tx_er;
    output gtx_clk;
    output lan_rst;
    reg lan_rst;
    input [7:0] udp_data;
    input udp_headadd;
    output [10:0] udp_addr;
    input [9:0] udp_length;
    output udp_rd;
    input udp_empty;
    output udp_over;
    input [31:0] s_des_ip;
    input [31:0] s_sou_ip;
    input [15:0] s_des_port;
    input [15:0] s_sou_port;
    input [47:0] s_sou_add;
    input [31:0] a_des_ip;
    input [47:0] a_des_add;
    input [31:0] r_des_ip;
    input [47:0] r_des_add;
    input r_empty;
    output r_rd;

wire ram_en;
wire[10:0] addr;
wire[7:0] data_out;
wire[47:0] desadd;
wire headadd;
wire[15:0] length;
wire latch;
wire full;

reg[23:0] counter;

always@(posedge clk125 or negedge rst)
begin
	if(!rst) begin
		  counter<=24'h0000_00;
		  lan_rst<=1'b0;
	end
	else begin
		counter<=counter+1;
		if(counter==24'hffff_ff)
		lan_rst<=1'b1;
	end
end

t_netlayer ua0 (
		.clk(clk125),
		.rst(rst),
		/******/
		.udp_over(udp_over),
		.udp_rd(udp_rd),
		.udp_empty(udp_empty),
		.udp_headadd(udp_headadd),
		.udp_length(udp_length),
		.udp_addr(udp_addr),
		.udp_data(udp_data),
		/*******/
		.s_des_ip(s_des_ip),
		.s_sou_ip(s_sou_ip),
		.s_des_port(s_des_port),
		.s_sou_port(s_sou_port),
		.s_sou_add(s_sou_add),
		/********/
		.a_des_ip(a_des_ip),
		.a_des_add(a_des_add),
		/********/
		.r_des_ip(r_des_ip),
		.r_des_add(r_des_add),
		.r_empty(r_empty),
		.r_rd(r_rd),
		/********/
		.ram_en(ram_en),
		.addr(addr),
		.data_out(data_out),
		.desadd(desadd),
		.headadd(headadd),
		.length(length),
		.latch(latch),
		.full(full)

		);


transmit ua1 ( 
    .clk125(clk125), 
    .rst(rst), 
    .souadd(s_sou_add), 
    .mode(mode), 
    .desadd(desadd), 
    .headadd(headadd), 
    .length(length), 
    .info_wr(latch), 
    .full(full), 
    .datain(data_out), 
    .addr(addr), 
    .ram_wr(ram_en), 
    .crs(crs), 
    .col(col), 
    .txd(txd), 
    .tx_en(tx_en), 
    .tx_er(tx_er), 
    .gtx_clk(gtx_clk), 
    .tran_ok(), 
    .late_col(), 
    .ex_col()
    );
endmodule