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uart.v
// *********************************************
//
// UART.v
//
// www.cmosexod.com
// 4/13/2001 (c) 2001
// Jeung Joon Lee
//
// Universal Asyhnchronous Receiver, Transmitter
// This is
sysid.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
fifosel.v
module FIFOSEL(addr,fifosel,ecs);
input[11:0] addr;
input ecs;
output fifosel;
wire tempa;
assign fifosel=((~ecs)&tempa);
assign tempa=(addr[11:5]==7'b1000000)?1'b1:1'b0;
endmodule
spiprocess.v
module spiprocess(clk,cpurd,cpuwr,cpusel,cpuindata,ramindata,outdata,addr,mosi,miso,reset,irq,CSN,SCK,RFirq,SendAddr,SendRDen,ReceiveData,ReceiveAddr,SendramCLK,ReceiveCLK,ReceiveWen,CE,sendfinishtest
ledrun.v
module LEDRun (reset,gclk,cpusel,cpurd,cpuwr,addr,indata,outdata,leddata);
input reset;
input [11:0]addr;
input [7:0]indata;
input gclk;
input cpusel;
input cpurd;
input cpuwr;
output [7:0
display.v
module display(clk,KEY1,KEY2,flag,LEDSN);
output [1:0]flag;
output [8:0]LEDSN;
input clk,KEY1,KEY2;
reg [1:0]flag;
reg [8:0]LEDSN;
parameter RED=0,YELLOW=1,GREEN=2;
integer cnt;
//initial cnt=
test.v
`timescale 10ns/1ns
module test;
reg clk,KEY1,KEY2;
wire [8:0]LEDSN1,LEDSN2;
wire RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2;
initial
begin
clk=0;
KEY1=1;
KEY2=1;
#180 KEY1=0;
#7 KEY1=1;
#8
main.v
module main(clk,KEY1,KEY2,LEDSN1,LEDSN2,RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2);
output RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2;
output [8:0]LEDSN1,LEDSN2;
input clk,KEY1,KEY2;
wire RED1,YELLOW1,
seriesport.v
//模块名：series_port.v
`include "uart_defines.v"
module series_port (reset,clk,MC_BD,MC_BA,mc_cs3,fpa_rw,MC_re,mc_irq4,
lpd_txd,ltp_txd,tpm_txd,outer_txd,
timescale.v
`timescale 1ns / 10ps