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V 的代码
clkgen.v
/////////////////////////////////////////////////////////////////////////////
module clkgen(phi1, phi2);
/////////////////////////////////////////////////////////////////////////////
output
dct.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, Parallel implementation
dctub.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, DCT unit block
zigzag.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Zig-Zag Unit
fdct.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Forward Discrete Cosine Transform and ZigZag unit
dctu.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform Unit
addersubtractor.v
// (C) 2004 Altera Corporation. All rights reserved. The design examples are
// being provided on an "as-is" basis and as an accommodation and therefore
// all warranties, representations or guar
out.v
module out(reset,cfloor,ccfloor);
input reset;
input[2:0] cfloor;
output[7:0] ccfloor;
reg[7:0] ccfloor;
always @(cfloor or reset)
begin
if(!reset)
begin
ccfloor=0;
end
else
begin