out.v

来自「一组两个电梯的控制器」· Verilog 代码 · 共 22 行

module out(reset,cfloor,ccfloor);
input reset;
input[2:0] cfloor;
output[7:0] ccfloor;
reg[7:0] ccfloor;

always @(cfloor or reset)
begin
	if(!reset)
	begin
		ccfloor=0;
	end
	else
	begin
	   
	        ccfloor=0;
	        ccfloor[cfloor]='b1;
	       
	end
end
endmodule