lift_top.v

来自「一组两个电梯的控制器」· Verilog 代码 · 共 42 行

`timescale 1ns/10ps
module lifttop(clk,reset,outCmd,inCmd1,inCmd2,
               out1,out2,status1,
               status2,open1,open2);
   input clk,reset;
   input[3:0] outCmd;
   input[2:0] inCmd1;
   input[2:0] inCmd2;
   wire[2:0] cfloor1;
   wire[2:0] cfloor2;
   output[7:0] out1;
   output[7:0] out2;
   output[1:0] status1;
   output[1:0] status2;
   output open1;
   output open2;

   
  
   wire[1:0] status1;
   wire[1:0] status2;
   wire[2:0] cmd1;
   wire[2:0] cmd2;
   wire LE1;
   wire LE2;
   
   
   scu scu1(.cfloor(cfloor1),.status(status1),.cmd(cmd1),
            .incmd(inCmd1),.reset(reset),.clk(clk),
            .load_enable(LE1),.open(open1));
   scu scu2(.cfloor(cfloor2),.status(status2),.cmd(cmd2),
            .incmd(inCmd2),.reset(reset),.clk(clk),
            .load_enable(LE2),.open(open2));

 centercontroler ee(.cmd1(cmd1),.cmd2(cmd2),.LE1(LE1),.LE2(LE2),.clk(clk),.reset(reset), .outCmd(outCmd),.cfloor1(cfloor1),.cfloor2(cfloor2),.status1(status1),.status2(status2));

   out o1(.reset(reset),.cfloor(cfloor1),.ccfloor(out1));
   out o2(.reset(reset),.cfloor(cfloor2),.ccfloor(out2));
endmodule