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gbt-v
%!PS-Adobe-3.0 Resource-CMap
%%DocumentNeededResources: ProcSet (CIDInit)
%%DocumentNeededResources: CMap (GBT-H)
%%IncludeResource: ProcSet (CIDInit)
%%IncludeResource: CMap (GBT-H)
%%BeginResou
dds.v
//
//
// This is just a little demo of DDS. It doesn't have any cool features
// or anything..
//
module dds (
clk,
reset,
din,
dout
);
parameter W = 12;
input
fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
timescale.v
`timescale 1ns / 10ps
ptos.v
module ptos(outenable,out_ps,reg_ps,outfifo,clkps);
output outenable;
output out_ps;
output [7:0] reg_ps;
input [7:0] outfifo;
input clkps;
reg out_ps;
reg [7:0] reg_ps;
reg [4
testall.v
module test_7;
// Signal declaration
reg clksp,in_sp;
wire [7:0] infifo,reg_sp;
reg clkps;
reg [7:0] outfifo;
wire [7:0] reg_ps;
wire out_ps,inenable,outenable;
// MUX instance
stop
test.v
module test_7;
// Signal declaration
reg clkps;
reg [7:0] outfifo;
wire [7:0] reg_ps;
wire out_ps;
// MUX instance
ptos exam(out_ps,reg_ps,outfifo,clkps);
// Apply Stimulus
initial
fifo.v
module fifo(outfifo,infifo,inenable,outenable);
output [7:0] outfifo;
input [7:0] infifo;
input inenable,outenable;
reg [7:0] outfifo;
reg [63:0] reg_fifo;
parameter pointer=0;
stop.v
module stop(inenable,infifo,reg_sp,clksp,in_sp);
output inenable;
output [7:0] infifo;
output [7:0] reg_sp;
input clksp;
input in_sp;
reg [7:0] infifo;
reg [7:0] reg_sp;
reg [4
dff.v
primitive dff(q,clock,d,reset);
output q;
input clock,d,reset;
reg q;
table
// clock d reset q-1 q
? ? 1 : ? : 0; // reset
r 0 0 : ? : 0; // set 0 (rise)
r 1 0 : ?