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scan.v
#############################################################################
# U N R E G I S T E R E D C O P Y
#
# You are on day 85 of your 30 day trial period.
#
# This
jsq.v
module jsq(clk,rst,c);
input clk,rst;
output c;
reg c;
reg [3:0]out;
always @(posedge clk)
begin
if (!rst)
begin
out
transmit.v
module transmit(addr,nrz1_in,nrz2_in,nrz3_in,nrz_out);
input [1:0] addr;
input [11:0] nrz1_in,nrz2_in,nrz3_in;
output [11:0] nrz_out;
wire [11:0] nrz1_store,nrz2_store,nzr3_store;
reg [11:0] nr
count.v
module count (clk,clk_12);
input clk;
output clk_12;
wire clk_12;
reg [3:0]n;
assign clk_12=(n[3]==1'b1)?(~clk_12):clk_12;
always@(posedge clk)
n
v.htm
V
Functions - V
[index]
graycode.v
//-----------------------------------------------------------------------------------
//数值二进制表示转换为格雷码
//输入：data_in：十进制数值输入，位宽为4比特
// EN：转换输出使能信号，高电平有效
//输出：data_out：转换后的格雷码，位宽为4比特
//------------
regfile.v
// ARM 7 Register File
// Jeffrey J. Cook
// ** UNTESTED, BEWARE **
`timescale 1ns/100ps
`define ADDRLEN 4
`define DBUSLEN 32
`define FLAGSLEN 11
`define CPSRSEL 0
`define SPSRSEL 1
`define MODE_
booth.v
//Name: Tam N. Nguyen, Thinh le, & Long Pham
//Behave of Booth Multiplier.
`define MULT_NUM_STATE_BITS 2
`define MULT_IDLE 2'b00
`define MULT_SHIFT 2'b01
`define MULT_RESULT 2'b10
`timescale
armdatapath.v
// ARM Datapath Module
// Instantiates all other modules, to be used with ARM Controller
// Deanna Perry
// 4/3/00
// Updated by Matt Crum on 4/6/00 -- cleaned up parameter list and wire
//
armcontroller.v
//////////////////////////////////////////////////
// //
// ARM Controller Mixed Model //
// Revision History