jsq.v

来自「在公司做的TCM编解码程序」· Verilog 代码 · 共 24 行

module jsq(clk,rst,c);
input clk,rst;
output c;
reg c;
reg [3:0]out;
always @(posedge clk)
begin 
if (!rst)
begin
out<=4'b0;
c<=1'b0;
end
else if(out==11)
begin
out<=4'b0;
c<=1'b1;
end
else
c<=1'b0;
out<=out+1'b1;
end
endmodule