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找到约 10,000 项符合
V 的代码
test.v
`timescale 10ns/100ps
module testBench;
reg clock,d,reset;
dff d1(q,clock,d,reset); // module substantiation
always // clock
#10 clock=~clock;
initial begin // test procedur
testbench.v
`timescale 10ms/10us
module testBench;
parameter T=1.667;
reg clk,reset;
digitalClock m(clk,reset,dispH1,dispH0,dispM1,dispM0,dispS1,dispS0);
initial
begin
clk=0;reset=0;
#T
digitalclock.v
module digitalClock(clk,reset,dispH1,dispH0,dispM1,dispM0,dispS1,dispS0);
input clk,reset;
output [6:0]dispH1,dispH0,dispM1,dispM0,dispS1,dispS0;
reg [6:0]dispH1,dispH0,dispM1,dispM0,dispS1,disp
controller.v
`define L_word 16
module Controller(Load_words,Shift1,Shift2,Add,Sub,Ready,BEC,Start,clock,reset);
output Load_words,Shift1,Shift2,Add,Sub,Ready;
input Start,clock,reset;
input [2:0]BEC;
reg
datapath.v
`define L_word 16
module Datapath(product,BEC,word1,word2,Load_words,Shift1,Shift2,Add,Sub,clock,reset);
output [2*`L_word-1:0]product;
output [2:0]BEC;
input [`L_word-1:0]word1,word2;
input
testbench.v
`define L_word 16
`timescale 10ns/100ps
module testBench;
wire [2*`L_word-1:0]product;
wire Ready;
reg [`L_word-1:0]word1,word2;
reg Start,clock,reset;
reg [2*`L_word-1:0] expected;
re
sdram.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
cf.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function