testbench.v

verilog实现电子时钟模块

`timescale 10ms/10us
module testBench;
	parameter T=1.667;
	reg clk,reset;
	
	digitalClock m(clk,reset,dispH1,dispH0,dispM1,dispM0,dispS1,dispS0);
	
	initial
		begin
			clk=0;reset=0;
			#T reset=1;
			#T reset=0;
		end
	
	always #(T/2) clk=~clk;
endmodule