controller.v

verilog程序

`define L_word 16
module Controller(Load_words,Shift1,Shift2,Add,Sub,Ready,BEC,Start,clock,reset);
	output Load_words,Shift1,Shift2,Add,Sub,Ready;
	input Start,clock,reset;
	input [2:0]BEC;
	reg [4:0]state,next_state;
	parameter S_idle=0,S_1=1,S_2=2,S_3=3,S_4=4,S_5=5,S_6=6,S_7=7,S_8=8;
	parameter S_9=9,S_10=10,S_11=11,S_12=12,S_13=13,S_14=14,S_15=15,S_16=16,S_17=17;
	reg Load_words,Shift1,Shift2,Add,Sub;
	wire Ready=((state==S_idle)&&!reset)||(state==S_17);
	
	always @(posedge clock)
		if(reset)state<=S_idle;
		else state<=next_state;
	
	always @(state or Start or BEC)
		begin
			Load_words=0;Shift1=0;Shift2=0;Add=0;Sub=0;
			case(state)
				S_idle:	if(Start)begin Load_words=1;next_state=S_1;end
					else next_state=S_idle;
				S_1: case(BEC)
						0: begin Shift2=1;next_state=S_3;end
						2: begin Add=1;Shift2=1;next_state=S_3;end
						4: begin Shift1=1;next_state=S_2;end
						6: begin Sub=1;Shift2=1;next_state=S_3;end
						default: next_state=S_idle;
					endcase
				S_2: begin Sub=1;Shift1=1;next_state=S_3;end
				
				S_3: case(BEC)
						0,7: begin Shift2=1;		next_state=S_5;end
						1,2: begin Add=1;Shift2=1;	next_state=S_5;end
						3,4: begin Shift1=1;		next_state=S_4;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_5;end
					endcase				
				S_4: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_5;
					end
				
				S_5: case(BEC)
						0,7: begin Shift2=1;		next_state=S_7;end
						1,2: begin Add=1;Shift2=1;	next_state=S_7;end
						3,4: begin Shift1=1;		next_state=S_6;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_7;end
					endcase				
				S_6: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_7;
					end
				
				S_7: case(BEC)
						0,7: begin Shift2=1;		next_state=S_9;end
						1,2: begin Add=1;Shift2=1;	next_state=S_9;end
						3,4: begin Shift1=1;		next_state=S_8;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_9;end
					endcase				
				S_8: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_9;
					end
				
				S_9: case(BEC)
						0,7: begin Shift2=1;		next_state=S_11;end
						1,2: begin Add=1;Shift2=1;	next_state=S_11;end
						3,4: begin Shift1=1;		next_state=S_10;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_11;end
					endcase				
				S_10: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_11;
					end
				
				S_11: case(BEC)
						0,7: begin Shift2=1;		next_state=S_13;end
						1,2: begin Add=1;Shift2=1;	next_state=S_13;end
						3,4: begin Shift1=1;		next_state=S_12;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_13;end
					endcase				
				S_12: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_13;
					end
				
				S_13: case(BEC)
						0,7: begin Shift2=1;		next_state=S_15;end
						1,2: begin Add=1;Shift2=1;	next_state=S_15;end
						3,4: begin Shift1=1;		next_state=S_14;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_15;end
					endcase				
				S_14: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_15;
					end
				
				S_15: case(BEC)
						0,7: begin Shift2=1;		next_state=S_17;end
						1,2: begin Add=1;Shift2=1;	next_state=S_17;end
						3,4: begin Shift1=1;		next_state=S_16;end
						5,6: begin Sub=1;Shift2=1;	next_state=S_17;end
					endcase				
				S_16: begin
						if(BEC[1:0]==2'b01)Add=1;
						else Sub=1;
						Shift1=1;					next_state=S_17;
					end
				
				S_17: if(Start)begin Load_words=1;	next_state=S_1;end
					else next_state=S_17;
				
				default: next_state=S_idle;				
			endcase
		end
endmodule