digitalclock.v

来自「verilog实现电子时钟模块」· Verilog 代码 · 共 89 行

module digitalClock(clk,reset,dispH1,dispH0,dispM1,dispM0,dispS1,dispS0);
	input clk,reset;
	output [6:0]dispH1,dispH0,dispM1,dispM0,dispS1,dispS0;
	reg [6:0]dispH1,dispH0,dispM1,dispM0,dispS1,dispS0;
	reg [3:0]h1,h0,m1,m0,s1,s0;
	reg start;
	
	always @(h1 or h0 or m1 or m0 or s1 or s0)
		begin
			dispH1=disp(h1);
			dispH0=disp(h0);
			dispM1=disp(m1);
			dispM0=disp(m0);
			dispS1=disp(s1);
			dispS0=disp(s0);
		end
	
	always @(posedge clk)
		begin
			if(reset)
				begin
					start=1;
					h1<=0;h0<=0;
					m1<=0;m0<=0;
					s1<=0;s0<=0;
				end
			else
				begin					
					if(s0==9)s0<=0;
					else s0<=s0+1;
					
					if(s0==9)
						begin
							if(s1==5)s1<=0;
							else s1<=s1+1;
						end
					else s1<=s1;
					
					if(s1==5&&s0==9)
						begin
							if(m0==9)m0<=0;
							else m0<=m0+1;
						end
					else m0<=m0;
					
					if(m0==9&&s1==5&&s0==9)
						begin
							if(m1==5)m1<=0;
							else m1<=m1+1;
						end
					else m1<=m1;
					
					if(m1==5&&m0==9&&s1==5&&s0==9)
						begin
							if(h0==9||(h1==2&&h0==3))h0<=0;
							else h0<=h0+1;
						end
					else h0<=h0;
					
					if(m1==5&&m0==9&&s1==5&&s0==9&&(h0==9||(h1==2&&h0==3)))
						begin
							if(h1==2&&h0==3)h1<=0;
							else h1<=h1+1;
						end
					else h1<=h1;
				end
			
		if(start)
				repeat(59) @(posedge clk);
		end
	
	function [6:0]disp;
		input [3:0]d;
		begin
			case(d)
				4'd0: disp=7'b1111110;
				4'd1: disp=7'b0110000;
				4'd2: disp=7'b1101101;
				4'd3: disp=7'b1111001;
				4'd4: disp=7'b0110011;
				4'd5: disp=7'b1011011;
				4'd6: disp=7'b1011111;
				4'd7: disp=7'b1110000;					   
				4'd8: disp=7'b1111111;
				4'd9: disp=7'b1111011;
			endcase
		end
	endfunction
endmodule