datapath.v

verilog程序

`define L_word 16
module Datapath(product,BEC,word1,word2,Load_words,Shift1,Shift2,Add,Sub,clock,reset);
	output [2*`L_word-1:0]product;
	output [2:0]BEC;
	input [`L_word-1:0]word1,word2;
	input Load_words,Shift1,Shift2,Add,Sub,clock,reset;
	reg [2*`L_word-1:0]product,multiplicant;
	reg [`L_word-1:0]multiplier;
	reg temp;
	wire [2:0]BEC={multiplier[1:0],temp};
	
	
	always @(posedge clock or posedge reset)
		begin
			if(reset)
				begin
					multiplier<=0;temp<=0;multiplicant<=0;product<=0;
				end
			else if(Load_words)
				begin
					temp<=0;
					if(~word1[`L_word-1])multiplicant<=word1;
					else multiplicant<={-`L_word'b1,word1};
					multiplier<=word2;
					temp<=0;
					product<=0;
				end
			else if(Add&&Shift1)
				begin
					product<=product+multiplicant;
					{multiplier,temp}<={multiplier,temp}>>1;
					multiplicant<=multiplicant<<1;
				end
			else if(Sub&&Shift1)
				begin
					product<=product-multiplicant;
					{multiplier,temp}<={multiplier,temp}>>1;
					multiplicant<=multiplicant<<1;
				end
			else if(Add&&Shift2)
				begin
					product<=product+multiplicant;
					{multiplier,temp}<={multiplier,temp}>>2;
					multiplicant<=multiplicant<<2;
				end
			else if(Sub&&Shift2)
				begin
					product<=product-multiplicant;
					{multiplier,temp}<={multiplier,temp}>>2;
					multiplicant<=multiplicant<<2;
				end
			else if(Shift1)
				begin
					{multiplier,temp}<={multiplier,temp}>>1;
					multiplicant<=multiplicant<<1;
				end
			else if(Shift2)
				begin
					{multiplier,temp}<={multiplier,temp}>>2;
					multiplicant<=multiplicant<<2;
				end
		end
endmodule