testbench.v

verilog程序

`define L_word 16
`timescale 10ns/100ps

module testBench;
	wire [2*`L_word-1:0]product;
	wire Ready;
	reg [`L_word-1:0]word1,word2;
	reg Start,clock,reset;
	reg [2*`L_word-1:0] expected;
	reg error;
	
	Booth_Multiplier_STG m0(product,Ready,word1,word2,Start,clock,reset);
	
	always #5 clock=~clock;
	
	initial begin
			clock=0;
			error=0;
			Start=0;
			#1 reset=1;
			#1 reset=0;
			repeat(100)
				begin
					word1=$random%17'b10000000000000000;
					word2=$random%17'b10000000000000000;
					Start=1;
					#25 Start=0;
					case({word1[`L_word-1],word2[`L_word-1]})
						2'b00: expected=word1*word2;
						2'b01: begin expected=word1*(~{-`L_word'd1,word2}+1);expected=~expected+1;end
						2'b10: begin expected=(~{-`L_word'd1,word1}+1)*word2;expected=~expected+1;end
						2'b11: expected=(~{-`L_word'd1,word1}+1)*(~{-`L_word'd1,word2}+1);
					endcase
					#150;
					error=~(expected==product);
					#20;
				end
				#10 $finish;
		end
endmodule