test.v

来自「verilog实现」· Verilog 代码 · 共 21 行

`timescale 10ns/100ps
module testBench;
	reg clock,d,reset;
	dff d1(q,clock,d,reset);	// module substantiation
	
	always						// clock
		#10 clock=~clock;
		
	initial begin				// test procedure
		$monitor($time," clock= %b d= %b reset= %b q= %b",clock,d,reset,q);
		#1 clock=0;reset=0;
		#1 d=1;
		#1 reset=1;
		#2 reset=0;
		#7 d=0;
		#25 d=1;
		#20 reset=1;
		#2 reset=0;
		#10 $finish;
	end
endmodule