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V 的代码
timescale.v
`timescale 1ns / 10ps
tests.v
task show_errors;
begin
$display("\n");
$display(" +--------------------+");
$display(" | Total ERRORS: %0d |", error_cnt);
$display(" +----------
division_a.v
module division_A(pa,pb,clk,db,pareg,pbreg,beginning);
input clk,pa,pb;
output [7:0] db;
output pareg,pbreg,beginning;
reg pareg,pbreg,beginning;
reg [7:0] db;
assign state={pa,pb};
assign pres
adder.v
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: adder.v
//
divider.v
`timescale 1ns/100ps
module divider (remainder,
divider_finish,
clk,
rst,
start_div,
dividened,
divisor
vspi.v
// ----------------------------------------------------------------------
// Copyright 1997-1998 VAutomation Inc. Nashua NH USA.
// Visit HTTP://www.vautomation.com for mor details on our other
//
system.v
/////////////////////////////////////////////////////////////////////////
// Module system.v
// Hierarchy: None ( It is the master )
// Module function:
// Module system.v generates input signals fo
spusnoop.v
// Produced by /usr/class/ee272/bin/snoopgen from file s.in
// Remember to run Verilog with -x if any variables are subscripted
// 2 Clock phases: phi1 phi2
// Input, Verilog: decisions_b_s1, irsi
controller.v
////////////////////////////////////////////////////////////////////////////
// Module controller.v
// Hierarchy: chip_core.v
// Module function:
// Module controller.v provides several functions:
spu.v
////////////////////////////////////////////////////
// Module spu.v
// Hierarchy: decoder_core.v
// Module function:
// Module spu.v implements the register-exchange technique for tracing
// of