divider.v

来自「移位快速除法器」· Verilog 代码 · 共 74 行

`timescale 1ns/100ps
module divider (remainder,
                divider_finish,
                clk,
                rst,
                start_div,
                dividened,
                divisor
                );
  
  input clk;
  input rst;
  input start_div;
  input [31:0] dividened;
  input [31:0] divisor;
  
  output [31:0] remainder;
  output  divider_finish;
  
  reg [5:0] counter;
  reg [31:0] p;  //Store the divisor
  reg [31:0] remainder;
  reg [31:0] remainder_low;
  reg        divider_finish;
  reg  [1:0]  flag; 

  
  always@(posedge clk or negedge rst)
    if(~rst) begin
        counter <= 6'b0;
        remainder <= 32'b0;
        remainder_low <= 32'b0;
        p <= 32'b0;
        flag <= 2'b00;
        end
    else if(start_div)  //check if counter begin to count down 
                    //in the same period with start
         begin   
          counter <= 6'd32;
          remainder <= 32'b0;
          remainder_low <= dividened;        
          p <= divisor;      
          flag <= 2'b01;   //
          divider_finish <=0;
       end
         
     else if(counter!=0) begin
              remainder_low <= remainder_low<<1;        
              if({remainder[30:0],remainder_low[31]} >=p)  
                 remainder <= {remainder[31:0],remainder_low[31]}-p;
              else
                 remainder <= {remainder[31:0],remainder_low[31]};
              counter <= counter-1;
           end
           else if(flag==2'b01)begin
                  divider_finish <= 1;
                  flag <= flag+1;
                end
                else begin 
                  flag <= 2'b00; 
                  divider_finish <= 0;
                 end
                                     
                
 /*always@(posedge clk or negedge rst)
   if(!rst) begin 
       divider_finish <= 0;
     end     
   else if (flag==2'b10)
           divider_finish <= 1;
        else divider_finish <= 0; */

 endmodule