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V 的代码
apbtimer.v
// --========================================================================--
//
// Module : ApbTimer
//
// ----------------------------------------------------------------------------
apbgpio.v
// --========================================================================--
//
// Module : ApbGPIO
//
// ----------------------------------------------------------------------------
/
timescale.v
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v
rxdcache.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
encapsule.v
module encapsule(
clk,
rst,
/*****/
desadd,
souadd,
u_length,
u_headadd,
send.v
module send(
clk125,
rst,
mode,
/*******/
empty,
headadd,
length,
rd,
datain,
addr,
/*******/
txd,
tx_en,
tx_er,
/********/
col,
crs,
/*******/
tran_ok,
late_c
arp.v
module arp(
clk,
rst,
/****the interfrace to mac sublayer****/
data_o,
full,
/****the interface with the arp request receiver***
gigarecv.v
module gigarecv(
clk,
rxc,
rst,
rx_dv,
rx_er,
rxd,
transmit.v
module transmit(
clk125,
rst,
souadd,
mode,
/******/
desadd,
headadd,
ethernet.v
module ethernet(
clk125,
rxc,
rst,
lan_rst,
mode,
s_des_ip,
s_sou_mac