📄 encapsule.v
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module encapsule(
clk,
rst,
/*****/
desadd,
souadd,
u_length,
u_headadd,
u_empty,
u_rd,
u_addr,
datain,
/*****/
l_headadd,
l_length,
l_latch,
l_full,
l_addr,
l_ena,
dataout,
);
/* split 2K B block memory to 4 part, 512B/part, about 2 TS packet/part;
headadd is 2b, addr is 11b
*/
input clk;
input rst;
input[47:0] desadd;
input[47:0] souadd;
input[15:0] u_length;
input u_headadd;
input u_empty;
output u_rd;
reg u_rd;
output[10:0] u_addr;
reg[10:0] u_addr;
input[7:0] datain;
output l_headadd;
reg l_headadd;
output[9:0] l_length;
output l_latch;
reg l_latch;
input l_full;
output[10:0] l_addr;
reg[10:0] l_addr;
output l_ena;
reg l_ena;
output[7:0] dataout;
reg[7:0] dataout;
reg[7:0] cache;
reg[31:0] crc;
reg[9:0] counter;
reg[5:0] current;
reg[5:0] next;
wire[15:0] length;
parameter IDLE=6'h01, PRE=6'h02, DATA=6'h04,
PAD=6'h08, CRC=6'h10, LATCH=6'h20;
assign l_length=counter;
assign length=u_length+6;
always@(current or u_empty or u_length or counter or l_full)
begin
next=6'bxxxx_xx;
case(current)
IDLE: begin
if(!u_empty&&!l_full)
next=PRE;
else
next=IDLE;
end
PRE: begin
if(counter==8)
next=DATA;
else
next=PRE;
end
DATA: begin
if(counter==u_length+28) begin
if(u_length>39)
next=CRC;
else
next=PAD;
end
else
next=DATA;
end
PAD: begin
if(counter==68)
next=CRC;
else
next=PAD;
end
CRC: begin
if(counter==u_length+32&&u_length>39)
next=LATCH;
else if(counter==72&&u_length<=39)
next=LATCH;
else
next=CRC;
end
LATCH: begin
next=IDLE;
end
default: next=IDLE;
endcase
end
always@(posedge clk or negedge rst)
begin
if(!rst) current<=IDLE;
else current<=next;
end
/********************the counter***************/
always@(posedge clk or negedge rst)
begin
if(!rst) counter<=10'b0000_0000_00;
else begin
if(next==IDLE)
counter<=10'b0000_0000_00;
else if(next!=LATCH)
counter<=counter+1;
end
end
/**********************the u_rd***************/
always@(posedge clk or negedge rst)
begin
if(!rst) u_rd<=1'b0;
else begin
if(counter==1)
u_rd<=1'b1;
else
u_rd<=1'b0;
end
end
/******************the u_addr****************/
always@(posedge clk or negedge rst)
begin
if(!rst) u_addr<=11'h000;
else begin
case(next)
DATA: begin
if(counter==25)
u_addr<={u_headadd,10'h00};
else
u_addr<=u_addr+1;
end
default: u_addr<=11'h000;
endcase
end
end
/*********************the cache**************/
always@(posedge clk or negedge rst)
begin
if(!rst) cache<=8'h55;
else begin
case(next)
LATCH: cache<=8'h55;
default: begin
case(counter)
0: cache<=8'h55;
1: cache<=8'h55;
2: cache<=8'h55;
3: cache<=8'h55;
4: cache<=8'h55;
5: cache<=8'h55;
6: cache<=8'hd5;
7: cache<=desadd[47:40];
8: cache<=desadd[39:32];
9: cache<=desadd[31:24];
10:cache<=desadd[23:16];
11:cache<=desadd[15:8];
12:cache<=desadd[7:0];
13:cache<=souadd[47:40];
14:cache<=souadd[39:32];
15:cache<=souadd[31:24];
16:cache<=souadd[23:16];
17:cache<=souadd[15:8];
18:cache<=souadd[7:0];
19:cache<=length[15:8];
20:cache<=length[7:0];
21:cache<=8'haa; //the LLC protocal head
22:cache<=8'haa;
23:cache<=8'h03;
24:cache<=8'h00;
25:cache<=8'h00;
26:cache<=8'h00;
default: begin
if(u_length<40&&counter>(u_length+26))
cache<=8'h00;
else
cache<=datain;
end
endcase
end
endcase
end
end
/*************************the dataout*********************/
always@(posedge clk or negedge rst)
begin
if(!rst) dataout<=8'h00;
else begin
case(next)
IDLE,
LATCH: dataout<=8'h00;
CRC: begin
dataout<={crc[24],crc[25],crc[26],crc[27],crc[28],crc[29],crc[30],crc[31]}^8'hff;
end
default: dataout<=cache;
endcase
end
end
/***********************the l_latch, l_headaddr *********************/
always@(posedge clk or negedge rst)
begin
if(!rst) begin
l_latch<=1'b0;
l_headadd<=1'b0;
end
else begin
if(next==LATCH) begin
l_latch<=1'b1;
end
else l_latch<=1'b0;
if(next==IDLE&¤t==LATCH)
l_headadd<=l_headadd+1;
end
end
/*****************the l_addr&&l_ena****************************/
always@(posedge clk or negedge rst)
begin
if(!rst) begin
l_addr<=11'h000;
l_ena<=1'b0;
end
else begin
if(next==PRE&¤t==IDLE)
l_addr<={l_headadd,10'h000};
else
l_addr<=l_addr+1;
case(next)
IDLE,
LATCH: l_ena<=1'b0;
default: l_ena<=1'b1;
endcase
end
end
/*******************CRC procedure*******************/
always@(posedge clk or negedge rst)
begin
if(!rst) begin
crc<=32'hffff_ffff;
end
else begin
case(next)
DATA,
PAD: begin
crc[0] <= crc[30] ^ cache[7] ^ crc[24] ^ cache[1];
crc[1] <= crc[30] ^ crc[31] ^ cache[6] ^ cache[7] ^ crc[24] ^ cache[0] ^ crc[25] ^ cache[1];
crc[2] <= crc[30] ^ crc[31] ^ cache[5] ^ cache[6] ^ cache[7] ^ crc[24] ^ crc[25] ^ crc[26] ^ cache[0] ^ cache[1];
crc[3] <= cache[4] ^ crc[31] ^ cache[5] ^ cache[6] ^ crc[25] ^ crc[26] ^ crc[27] ^ cache[0];
crc[4] <= crc[30] ^ cache[4] ^ cache[5] ^ cache[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[28] ^ cache[1] ^ cache[3];
crc[5] <= crc[30] ^ cache[4] ^ crc[31] ^ cache[6] ^ cache[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[29] ^ cache[0] ^ cache[1] ^ cache[2] ^ cache[3];
crc[6] <= crc[30] ^ crc[31] ^ cache[5] ^ cache[6] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ cache[0] ^ cache[1] ^ cache[2] ^ cache[3];
crc[7] <= cache[4] ^ cache[5] ^ crc[31] ^ cache[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ cache[0] ^ cache[2];
crc[8] <= cache[4] ^ cache[6] ^ cache[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[0] ^ cache[3];
crc[9] <= cache[5] ^ cache[6] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ cache[2] ^ crc[1] ^ cache[3];
crc[10] <= cache[4] ^ cache[5] ^ cache[7] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ cache[2] ^ crc[2];
crc[11] <= cache[4] ^ crc[3] ^ cache[6] ^ cache[7] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ cache[3];
crc[12] <= crc[30] ^ cache[5] ^ crc[4] ^ cache[6] ^ cache[7] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ cache[1] ^ cache[2] ^ cache[3];
crc[13] <= cache[4] ^ crc[30] ^ crc[31] ^ cache[5] ^ cache[6] ^ crc[5] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[29] ^ cache[0] ^ cache[1] ^ cache[2];
crc[14] <= cache[4] ^ crc[30] ^ cache[5] ^ crc[31] ^ crc[6] ^ crc[26] ^ crc[27] ^ crc[28] ^ cache[0] ^ cache[1] ^ cache[3];
crc[15] <= cache[4] ^ crc[31] ^ crc[7] ^ crc[27] ^ crc[28] ^ crc[29] ^ cache[0] ^ cache[2] ^ cache[3];
crc[16] <= cache[7] ^ crc[24] ^ crc[8] ^ crc[28] ^ crc[29] ^ cache[2] ^ cache[3];
crc[17] <= crc[30] ^ cache[6] ^ crc[25] ^ crc[9] ^ crc[29] ^ cache[1] ^ cache[2];
crc[18] <= crc[30] ^ cache[5] ^ crc[31] ^ crc[26] ^ cache[0] ^ cache[1] ^ crc[10];
crc[19] <= cache[4] ^ crc[31] ^ crc[27] ^ cache[0] ^ crc[11];
crc[20] <= crc[12] ^ crc[28] ^ cache[3];
crc[21] <= crc[13] ^ crc[29] ^ cache[2];
crc[22] <= crc[14] ^ cache[7] ^ crc[24];
crc[23] <= crc[30] ^ cache[6] ^ cache[7] ^ crc[24] ^ crc[15] ^ crc[25] ^ cache[1];
crc[24] <= crc[31] ^ cache[5] ^ cache[6] ^ crc[25] ^ crc[16] ^ crc[26] ^ cache[0];
crc[25] <= cache[4] ^ cache[5] ^ crc[26] ^ crc[17] ^ crc[27];
crc[26] <= crc[30] ^ cache[4] ^ cache[7] ^ crc[24] ^ crc[27] ^ crc[18] ^ crc[28] ^ cache[1] ^ cache[3];
crc[27] <= crc[31] ^ cache[6] ^ crc[25] ^ crc[28] ^ crc[19] ^ crc[29] ^ cache[0] ^ cache[2] ^ cache[3];
crc[28] <= crc[30] ^ cache[5] ^ crc[26] ^ crc[29] ^ cache[1] ^ cache[2] ^ crc[20];
crc[29] <= cache[4] ^ crc[30] ^ crc[21] ^ crc[31] ^ crc[27] ^ cache[0] ^ cache[1];
crc[30] <= crc[31] ^ crc[22] ^ crc[28] ^ cache[0] ^ cache[3];
crc[31] <= crc[23] ^ crc[29] ^ cache[2];
end
CRC: begin
crc[31:0]<={crc[23:0],8'hff};
end
default: begin
crc[31:0]<=32'hffff_ffff;
end
endcase
end
end
endmodule
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