apbgpio.v

PowerFull Apb GPIO Controller

//  --========================================================================--
//
//  Module      : ApbGPIO
//
//  ----------------------------------------------------------------------------
//  Purpose     : Provides memory mapped locations for reading up to 32 input
//                lines and for controlling up to 32 output lines.
//
//                There are two registers in this block:
//                  - Out Control Reg (write only)
//                  - In Status Reg   (cleared on read)
//
//                A write to any address in this APB slot write the Out Control Reg.
//                A read from any address in this APB slot reads the In Status Reg.
//
//  --========================================================================--

`timescale 1ns/1ps

module ApbGPIO (
    PCLK,
    PRESETn,
    PENABLE,
    PSEL,
    PADDR,
    PWRITE,
    PWDATA,
    dataIn,
    PRDATA,
    dataOut
    );

    parameter NUM_INPUTS  = 32; // Number of inputs.  Range: 1 - 32.
    parameter NUM_OUTPUTS = 32; // Number of outputs. Range: 1 - 32.

    input                    PCLK;
    input                    PRESETn;
    input                    PENABLE;
    input                    PSEL;
    input              [5:2] PADDR;
    input                    PWRITE;
    input  [NUM_OUTPUTS-1:0] PWDATA;
    input   [NUM_INPUTS-1:0] dataIn;

    output  [NUM_INPUTS-1:0] PRDATA;
    output [NUM_OUTPUTS-1:0] dataOut;

    // Input/Output Signals
    wire                     PCLK;
    wire                     PRESETn;
    wire                     PENABLE;
    wire                     PSEL;
    wire               [5:2] PADDR;
    wire                     PWRITE;
    wire   [NUM_OUTPUTS-1:0] PWDATA;
    reg     [NUM_INPUTS-1:0] PRDATA;

    reg    [NUM_OUTPUTS-1:0] dataOut;

    // Internal Signals
    wire                     NxtPrdataEn;    //  Valid GPIO read
    wire                     regWrReq;
    reg     [NUM_INPUTS-1:0] inData;
    reg     [NUM_INPUTS-1:0] inData_s1;
    reg     [NUM_INPUTS-1:0] inData_s2;

    //------------------------------------------------------------------------------
    // Out Control Register
    //------------------------------------------------------------------------------
    assign regWrReq = ( PSEL && PWRITE && !PENABLE ) ? 1'b1 : 1'b0;

    always @ ( posedge PCLK or negedge PRESETn )
    begin
        if ( !PRESETn )
            dataOut <= 0;
        else
            if ( regWrReq )
                dataOut <= PWDATA[NUM_OUTPUTS-1:0];
    end

    //------------------------------------------------------------------------------
    // PRDATA generation
    //------------------------------------------------------------------------------
    // Address decoding for register reads.
    assign NxtPrdataEn = ( PSEL & !PWRITE & !PENABLE );

    // PRDATA output register
    always @ ( posedge PCLK or negedge PRESETn )
    begin
        if (!PRESETn)
            PRDATA <= 0;
        else
            PRDATA <= inData;
    end

    always @ ( posedge PCLK or negedge PRESETn )
    begin
        if ( !PRESETn )
        begin
            inData    <= 0;
            inData_s1 <= 0;
            inData_s2 <= 0;
        end
        else
        begin
            inData_s1 <= dataIn;
            inData_s2 <= inData_s1;

            if ( NxtPrdataEn )
                inData <= 0;
            else
                inData <= ( inData_s1 & inData_s2 );
        end
    end

endmodule

// --================================= End ===================================--