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V 的代码
spu.v
////////////////////////////////////////////////////
// Module spu.v
// Hierarchy: decoder_core.v
// Module function:
// Module spu.v implements the register-exchange technique for tracing
// of
clkgen.v
/////////////////////////////////////////////////////////////////////////////
module clkgen(phi1, phi2);
/////////////////////////////////////////////////////////////////////////////
output
mzk.v
module mzk(clksource,clk,baudsetting,mod_mzk_out,start,demod_mzkin);
input clksource,start,demod_mzkin;
input [1:0]baudsetting;
output clk,mod_mzkout;
reg clk,mod_mzkout;
reg [10:0]
serial.v
//-----------------------------------------------------------------------------
// module: serial.vhd
// This file contains modules for serial I/O.
//
// OVERVIEW of contents: The clock generator
top.v
//-----------------------------------------------------------------------------
//
// Author: John Clayton
// Date : Nov. 5, 2001
// Update: Nov. 5, 2001 Obtained this file from "build_9b" pr
filter.v
//`include "reg8.v"
module filter(out_data,in_data,clk);
output[9:0] out_data;
input [7:0] in_data;
input clk;
//reg[9:0] out_data;
wire clr,en;
assign en=1;assign clr=0;
reg[7:0] in_data1
fifo.v
module fifo(clk,reset,r_en,w_en,ov,din,dout);
input reset,clk,w_en,r_en;
input [7:0] din;
output[7:0] dout;
output ov;
reg flag;
reg[5:0] count;
reg[5:0] wadd;
reg[5:0] radd;
reg[7:0]
scratch.v
module multiplexor(in, select, out);
parameter width = 1, select_bits = 1;
input [width-1:0][(1
fft.v
module sequential__adder(a, b, sum, clock);
parameter width = 1;
input [width-1:0] a;
input [width-1:0] b;
input clock;
output [width-1:0] sum;
reg [width-1:0] sum;
always @(posedge
baud.v
//
// BAUD.v
//
// www.cmosexod.com
// 4/13/2001 (c) 2001
// Jeung Joon Lee
//
// This is the "baud-rate-genrator"
// The "baud_clk" is the output clock feeding the
// receiver and transmit