fifo.v

实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能

module fifo(clk,reset,r_en,w_en,ov,din,dout);

 input reset,clk,w_en,r_en;
 input [7:0] din;
 output[7:0] dout;
 output ov;
 
 

 reg flag;
 reg[5:0] count;
 reg[5:0] wadd;
 reg[5:0] radd;
 reg[7:0] ram[15:0];
 reg[7:0] dout;
 reg  ov;

always @(posedge clk or negedge reset)
    begin
       if(~reset)
            wadd<=0;
       else if(w_en & flag)
           wadd<=wadd+1;
             
       else
              wadd<=wadd;

     end
      
      
always @(posedge clk or negedge reset)
     begin
        if(~reset)
          radd<=0;
        else if(r_en & flag)
            radd<=radd+1;
        else 
             radd<=0;
     end
     
     
     

always @(posedge clk or negedge reset)
       begin
          if (~reset)
              count<=0;
          else if(w_en)
               begin
                  if(count==16)
                  begin
                       count<=0; 
                       flag<=0;
                       ov<=1;
                   end
                   else
                     begin
                       count<=count+1;
                       flag<=1;
                     end
               end
             else if(r_en )
                begin    
                 if(count==0)
                     begin
                        ov<=0;
                        flag<=0;
                      end
                     else
                        count<=count-1;
                         flag<=1;
               end
          else
                 flag<=1;
         end
            
 always @(posedge clk)
     begin
         if(w_en)
             ram[wadd]<=din;
          else 
             dout<=ram[radd];
              
      end
          
         
endmodule