send.v

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

module send(
	clk125,
	rst,
	mode,
	/*******/
	empty,
	headadd,
	length,
	rd,
	datain,
	addr,
	/*******/
	txd,
	tx_en,
	tx_er,	
	/********/
	col,
	crs,
	/*******/
	tran_ok,
	late_col,
	ex_col	
	);
	
    input clk125;
    input rst;
    input mode;
    
    input empty;
    input headadd;
    input[9:0] length;
    output rd;
    reg rd;
    input[7:0] datain;
    output[10:0] addr;
    reg[10:0] addr;
    
    output[7:0] txd;  
    output tx_en;
    reg tx_en;
    output tx_er;
    reg tx_er;
   
    
    input col;
    input crs;
    
    output tran_ok;
    reg tran_ok;
    output late_col;
    reg late_col;
    output ex_col;
    reg ex_col;
    
    
    reg[9:0] counter;
    reg[9:0] j_counter;    
    reg[3:0] jam_number;
    reg[3:0] busy_counter;
    reg out_jam;
    reg[3:0] over_counter;
    
    reg[8:0] current;
    reg[8:0] next;
    
    parameter IDLE=1, RD=2, GET=4, LOAD=8,
              SEND=16, SEND_E=32, JAM=64, OVER=128,
              BUSY=256;

assign txd=datain;             
always@(current or crs or empty or mode or col or length or counter
        or busy_counter or jam_number or out_jam or over_counter)
begin
	next=9'bxxxx_xxxx_x;
	case(current)
	IDLE: begin
		if(!empty)
		next=RD;
		else
		next=IDLE;
	end
	RD: next=GET;
	GET: next=LOAD;
	LOAD: begin
		if(!mode&&crs)
		next=BUSY;	
		else
		next=SEND;
	end 
	BUSY: begin
		if(busy_counter==15&&!crs)
		next=SEND;
		else
		next=BUSY;
	end
	SEND: begin
		if(mode) begin
			if(length==counter)
			next=OVER;
			else
			next=SEND;
		end
		else begin
			if(col)
			next=JAM;
			else if(length==counter) begin
				if(length>511)
				next=OVER;
				else
				next=SEND_E;
			end
			else
			next=SEND;
		end
	end
	SEND_E: begin
		if(counter==511)
		next=OVER;
		else
		next=SEND_E;
	end
	JAM: begin
		if(out_jam) begin
			if(jam_number==15)
			next=IDLE;
			else
			next=LOAD;
		end
		else
		next=JAM;
	end
	OVER: begin
		if(over_counter==11)
		next=IDLE;
		else
		next=OVER;
	end
	default: next=IDLE;
	endcase
end
		
always@(posedge clk125 or negedge rst)
begin
	if(!rst) current<=IDLE;
	else current<=next;
end

/**************counter********************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) counter<=10'h000;
	else begin
		case(next)
		SEND,
		SEND_E: counter<=counter+1;
		default: counter<=10'h000;
		endcase
	end
end
/*************	j_counter**************
***********actually, j_counter should be used*******
 the truncated binary back off alogrithm****/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) j_counter<=10'h000;
	else begin
		if(next==JAM)
		j_counter<=j_counter+1;
		else
		j_counter<=10'h000;
	end
end
/**********************the out_jam***************/
always@(posedge clk125 or negedge rst)	
begin
	if(!rst) out_jam<=1'b0;
	else begin
		if(next==JAM&&j_counter==10'h3ff)
		out_jam<=1'b1;
		else
		out_jam<=1'b0;
	end
end
/*****************jam_number***************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) jam_number<=4'h0;
	else begin
		if(next==JAM&&current!=JAM)
		jam_number<=jam_number+1;
		else if(next==IDLE)
		jam_number<=4'h0;
	end
end
/*****************busy_counter************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) busy_counter<=4'b0000;
	else begin
		if(next==BUSY)
		busy_counter<=busy_counter+1;
		else
		busy_counter<=4'b0000;
	end
end
/**************over counter*******************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) over_counter<=4'h000;
	else begin
		if(next==OVER)
		over_counter<=over_counter+1;
		else
		over_counter<=4'h000;
	end
end
/****************rd*******************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) rd<=1'b0;
	else begin
		if(next==RD)
		rd<=1'b1;
		else
		rd<=1'b0;
	end
end
/*****************the addr****************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) addr<=11'b0000_0000_000;
	else begin
		case(next)
		LOAD: addr<={headadd,10'h000};
		SEND: addr<=addr+1;
		default: addr<=11'b0000_0000_000;
		endcase
	end
end
/***************the txd, tx_en**************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) begin
		tx_en<=1'b0;	
	end
	else begin
		case(next)
		SEND:begin 
			tx_en<=1'b1;
		end
		JAM: begin 
			if(j_counter<12)
			tx_en<=1'b1;
			else
			tx_en<=1'b0;
		end
		default: begin 
			tx_en<=1'b0;
		end
		endcase
	end
end
/***************tx_er***********************/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) tx_er<=1'b0;
	else begin
		if(next==SEND_E)
		tx_er<=1'b1;
		else
		tx_er<=1'b0;
	end
end
/******************tran_ok, late_col, ext_col**********/
always@(posedge clk125 or negedge rst)
begin
	if(!rst) begin
		tran_ok<=1'b0;
		late_col<=1'b0;
		ex_col<=1'b0;
	end
	else begin
		if(next==OVER&&current!=OVER)
		tran_ok<=1'b1;
		else
		tran_ok<=1'b0;
		
		if(next==JAM&&current!=JAM)
		late_col<=1'b1;
		else
		late_col<=1'b0;
		
		if(next==JAM&&current!=JAM&&jam_number==14)
		ex_col<=1'b1;
		else
		ex_col<=1'b0;
	end
end
endmodule