gigarecv.v

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

module gigarecv(
                   clk,
                   rxc,
                   rst,
                   rx_dv,
                   rx_er,                   
                   rxd,
                   dataout,
                   out_en,
                   a_des_add,
                   a_des_ip,
                   r_des_add,
                   r_des_ip,
                   r_empty,
                   r_rd,
			 souadd
                   );
    input clk;
    input rxc;
    input rst;
    input rx_dv;
    input rx_er;
    input [7:0] rxd;
    output [7:0] dataout;
    output out_en;
    output [47:0] a_des_add;
    output [31:0] a_des_ip;
    output [47:0] r_des_add;
    output [31:0] r_des_ip;
    output r_empty;
    input r_rd;
    input[47:0] souadd;

wire[12:0] addr;
wire[7:0] p_data;
wire p_empty;
wire[10:0] length;
wire[4:0] headadd;
wire indx_rd;
wire rxc1;
wire rxc2;




receive uu0   (
               .clk(clk),
               .rst(rst),
               .add(addr),
               .dataout(p_data),
               /******/
               .empty(p_empty),
               .indx({headadd,length}),
               .index_en(indx_rd),
               /******/
               .rxc(rxc),
               .rx_dv(rx_dv),
               .rx_er(rx_er),
               .rxd(rxd),
		   .souadd(souadd),
               .error()
               );
               
               
r_netlayer uu1   (
                .clk(clk),
                .rst(rst),
                .a_des_add(a_des_add),
                .a_des_ip(a_des_ip),
                .r_des_add(r_des_add),
                .r_des_ip(r_des_ip),
                .r_empty(r_empty),
                .r_rd(r_rd),
                .dataout(dataout),
                .out_en(out_en),
                .headadd(headadd),
                .length(length),
                .indx_empty(p_empty),
                .indx_rd(indx_rd),
                .data_in(p_data),
                .addr(addr)
                );

endmodule