count.v

来自「在公司做的TCM编解码程序」· Verilog 代码 · 共 14 行

module count (clk,clk_12);

input clk;
output clk_12;
wire  clk_12;

reg [3:0]n;

assign clk_12=(n[3]==1'b1)?(~clk_12):clk_12;
always@(posedge clk)

n<=n+4'b1;
endmodule