transmit.v

来自「在公司做的TCM编解码程序」· Verilog 代码 · 共 53 行

module transmit(addr,nrz1_in,nrz2_in,nrz3_in,nrz_out);
input [1:0] addr;
input [11:0] nrz1_in,nrz2_in,nrz3_in;
output [11:0] nrz_out;

wire [11:0] nrz1_store,nrz2_store,nzr3_store;
reg [11:0] nrz_out;


assign 		nrz1_store=nrz1_in;
assign 		nrz2_store=nrz2_in;
assign 		nrz3_store=nrz3_in;

always@(addr)
begin
//		nrz1_store=nrz1_in;
//		nrz2_store=nrz2_in;
//		nrz3_store=nrz3_in;
	case(addr)
		2'b00:nrz_out=nrz1_store;
		2'b01:nrz_out=nrz2_store;
		2'b10:nrz_out=nrz3_store;
	default:nrz_out=12'h?;
	endcase
end
endmodule

/*
module transmit(addr,nrz1_in,nrz2_in,nrz3_in,nrz_out);
input [1:0] addr;
input [11:0] nrz1_in,nrz2_in,nrz3_in;
output [11:0] nrz_out;

//reg [11:0] nrz1_store,nrz2_store,nzr3_store;
reg [11:0] nrz_out;

always@(addr)
begin
//		nrz1_store=nrz1_in;
//		nrz2_store=nrz2_in;
//		nrz3_store=nrz3_in;
	case(addr)
		2'b00:nrz_out=nrz1_in;
		2'b01:nrz_out=nrz2_in;
		2'b10:nrz_out=nrz3_in;
	default:nrz_out=12'h?;
	endcase
end
endmodule
*/