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V 的代码
memoryside.v
// Verilog source file for the MemoryASM
// Written by Chris Fester 3-28-00
// This represents the "memory controller" side of the Memory Interface. It runs
// with the assumption that it is being co
timescale.v
`timescale 1ns / 10ps
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
altclklock.v
// megafunction wizard: %ALTCLKLOCK%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclklock
// ============================================================
// File Name: PLL1.v
// Me
params.v
// global parameters for Viterbi Decoder
// decoder specs :
// K = 9,
// RATE = 1/2,
// DEPTH = 63,
// number of ACS = 4
// PARAMETER VALUES BITS ORDER WIDTH PARS
// input
decoder.v
`include "params.v"
/*-----------------------------------*/
// Module : VITERBIDECODER
// File : decoder.v
// Description : Top Level Module of Viterbi Decoder
// Simulator : Modelsim 4.6 / W
dff.v
/******************************************************/
module pDFF(DATA,QOUT,CLOCK,RESET);
/******************************************************/
parameter WIDTH = 1;
input [WIDTH-1:0] D
ram.v
`include "params.v"
/*-----------------------------------*/
// Module : RAMs
// File : ram.v
// Description : The RAMs definition.
// -- mainly used on functional simulation only
// Simula
control.v
`include "params.v"
/*-----------------------------------*/
// Module : CONTROL
// File : control.v
// Description : Description of Control Unit in Viterbi Decoder
// Simulator : Modelsim