main.v

来自「基于Maxplus2的Verilog编程」· Verilog 代码 · 共 12 行

module main(clk,KEY1,KEY2,LEDSN1,LEDSN2,RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2);
output RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2;
output [8:0]LEDSN1,LEDSN2;
input clk,KEY1,KEY2;
wire RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2;
wire [1:0]flag1,flag2;
wire [8:0]LEDSN1,LEDSN2;
display D1(clk,KEY1,KEY2,flag1,LEDSN1);
display2 D2(clk,KEY1,KEY2,flag2,LEDSN2);
LED_control L1(flag1,RED1,YELLOW1,GREEN1);
LED_control L2(flag2,RED2,YELLOW2,GREEN2);
endmodule