test.v

基于Maxplus2的Verilog编程

`timescale 10ns/1ns
module test;
reg clk,KEY1,KEY2;
wire [8:0]LEDSN1,LEDSN2;
wire RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2;
initial
begin 
clk=0;
KEY1=1;
KEY2=1;
#180 KEY1=0;
#7 KEY1=1;
#8 KEY2=0;
#5 KEY2=1;
#220 KEY1=0;
#7 KEY1=1;
end
always
 #2 clk=~clk;
 main M1(clk,KEY1,KEY2,LEDSN1,LEDSN2,RED1,YELLOW1,GREEN1,RED2,YELLOW2,GREEN2);
 endmodule