protocol.v

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

module protocol(
                clk,
                rst,
                p_headadd,
                p_length,
                p_rd,
                p_empty,
                p_data,
                p_addr,
                p_des_add,
                arp_data,
                arp_en,
                ip_data,
                ip_en
                );
    input clk;
    input rst;
    input[4:0] p_headadd;
    input[10:0] p_length;
    output p_rd; 
    reg p_rd;
    input p_empty;
    input [7:0] p_data;
    output[12:0] p_addr;
    reg[12:0] p_addr; //the ram capacity is 8K
    output [47:0] p_des_add;
    reg[47:0] p_des_add;
    output [7:0] arp_data;
    reg[7:0] arp_data;
    output arp_en;
    reg arp_en;
    output [7:0] ip_data;
    reg [7:0]ip_data;
    output ip_en;
    reg ip_en;
    
    reg[7:0] current;
    reg[7:0] next;
    
    reg[10:0] counter;
    reg[2:0] GET_counter;
    reg[1:0] CON_counter;
    
    reg[15:0] len_type;

    parameter IDLE=8'h01, MAC=8'h02, IEEE=8'h04, IP=8'h08,
              ARP=8'h10,  UNK=8'h20, GET=8'h40, CON=8'h80;

             
always@(current or p_empty or p_length or counter or GET_counter
        or len_type or CON_counter)
begin
	next=8'hxx;
	case(current)
	IDLE: begin
		if(!p_empty)
		next=GET;
		else
		next=IDLE;
	end
	GET: begin
		if(GET_counter==4)
		next=MAC;
		else
		next=GET;
	end
	MAC: begin
		if(counter==12)
		next=CON;
		else
		next=MAC;
	end
	CON: begin
		if(CON_counter==2)begin
			if(len_type<1536)
			next=IEEE;
			else if(len_type==16'h0806)
			next=ARP;
			else if(len_type==16'h0800)
			next=IP;
			else
			next=UNK;
		end
		else
		next=CON;
	end
	IEEE: begin
		if(counter==20)
		next=CON;
		else
		next=IEEE;
	end
	IP: begin
		if(counter==p_length)
		next=IDLE;
		else
		next=IP;
	end
	ARP: begin
		if(counter==p_length)
		next=IDLE;
		else
		next=ARP;
	end
	UNK: begin
		if(counter==p_length)
		next=IDLE;
		else
		next=UNK;
	end
	default: next=IDLE;
	endcase
end

always@(posedge clk or negedge rst)
begin
	if(!rst) current<=IDLE;
	else current<=next;
end

/**************get GET_counter and rd and addr**************/
always@(posedge clk or negedge rst)
begin
	if(!rst) begin
		GET_counter<=3'b000;
		p_rd<=1'b0;
		p_addr<=13'h0000;
	end
	else begin
		if(next==GET) begin
			GET_counter<=GET_counter+1;
			case(GET_counter)
			0: p_rd<=1'b1;
			1: p_rd<=1'b0;
			2: p_addr<={p_headadd,8'h00};
			3: p_addr<=p_addr+1;
			endcase
		end
		else begin
			GET_counter<=3'b000;
			p_rd<=1'b0;
			case(next)
			IDLE: p_addr<=13'h0000;
			default:
			p_addr<=p_addr+1;
			endcase
		end
	end
end
/*******************the CON_counter***************/
always@(posedge clk or negedge rst)
begin
	if(!rst) CON_counter<=2'b00;
	else begin
		if(next==CON)
		CON_counter<=CON_counter+1;
		else
		CON_counter<=2'b00;
	end
end
/*********************the counter****************/
always@(posedge clk or negedge rst)
begin
	if(!rst) counter<=11'h000;
	else begin
		case(next)
		IDLE,
		GET: counter<=11'h000;
		default: counter<=counter+1;
		endcase
	end
end
/****************the MAC********************/
always@(posedge clk or negedge rst)
begin
	if(!rst) p_des_add<=48'h0000_0000_0000;
	else begin
		if(next==MAC) begin
			case(counter)
			6,
			7,
			8,
			9,
			10,
			11:p_des_add<={p_des_add[39:0],p_data};
			endcase
		end
	end
end
/*******************the length_type*************/
always@(posedge clk or negedge rst)
begin
	if(!rst) len_type<=16'h0000;
	else begin
		if(next==CON)
		len_type<={len_type[7:0],p_data};
	end
end
/*****************the ARP or IP output data*************/
always@(posedge clk or negedge rst)
begin
	if(!rst) begin
		arp_data<=8'h00;
		arp_en<=1'b0;
		ip_data<=8'h00;
		ip_en<=1'b0;
	end
	else begin
		case(next)
		ARP: begin
			arp_data<=p_data;
			arp_en<=1'b1;
			ip_en<=1'b0;
		end
		IP:begin
			arp_en<=1'b0;
			ip_data<=p_data;
			ip_en<=1'b1;
		end
		default: begin
			ip_en<=1'b0;
			arp_en<=1'b0;
		end
		endcase
	end
end
endmodule