lcdfinal.v

LCD显示

//`include "F:\jeffie\quartus\lcdfinal\lcdfinal.v"
//`include "F:\jeffie\quartus\lcdfinal\LCD_TEST.v"
//`include "F:\jeffie\quartus\lcdfinal\Reset_Delay.v"

module lcdfinal
	(
		////////////////////	Clock Input	 	////////////////////	 
	
		CLOCK_50,						//	50 MHz
        SW,
	
		////////////////////	LCD Module 16X2		////////////////
		LCD_ON,							//	LCD Power ON/OFF
		LCD_BLON,						//	LCD Back Light ON/OFF
		LCD_RW,							//	LCD Read/Write Select, 0 = Write, 1 = Read
		LCD_EN,							//	LCD Enable
		LCD_RS,							//	LCD Command/Data Select, 0 = Command, 1 = Data
		LCD_DATA,						//	LCD Data bus 8 bits
		////////////////////	LED Module 		////////////////
        HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7
		
	);

////////////////////////	Clock Input	 	////////////////////////

input			CLOCK_50;				//	50 MHz
input           [4:0]SW;
//output          [4:0]LCD_XX;

////////////////////	LCD Module 16X2	////////////////////////////
inout	[7:0]	LCD_DATA;				//	LCD Data bus 8 bits
output			LCD_ON;					//	LCD Power ON/OFF
output			LCD_BLON;				//	LCD Back Light ON/OFF
output			LCD_RW;					//	LCD Read/Write Select, 0 = Write, 1 = Read
output			LCD_EN;					//	LCD Enable
output			LCD_RS;					//	LCD Command/Data Select, 0 = Command, 1 = Data
////////////////////	LED Module 		////////////////
output [6:0]HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
assign HEX0=7'bzzzzzzz,HEX1=7'bzzzzzzz,HEX2=7'bzzzzzzz,HEX3=7'bzzzzzzz,HEX4=7'bzzzzzzz,HEX5=7'bzzzzzzz,HEX6=7'bzzzzzzz,HEX7=7'bzzzzzzz;

//	LCD ON
assign	LCD_ON		=	1'b1;
assign	LCD_BLON	=	1'b0;

wire		DLY_RST;
wire		[4:0]LCD_XX;

Reset_Delay			r0	(	.iCLK(CLOCK_50),.oRESET(DLY_RST)	);	

LCD_TEST_initial   u0(.iCLK(CLOCK_50),
                    .iRST_N(DLY_RST),
                    .LCD_DATA(LCD_DATA),
                    .LCD_RW(LCD_RW),
                    .LCD_EN(LCD_EN),
                    .LCD_RS(LCD_RS),
                    .LCD_XX(LCD_XX));

always @(SW)

 begin
    case(SW)
      5'b00000:LCD_XX=5'b00001;
      5'b00010:LCD_XX=5'b00010;
      5'b00100:LCD_XX=5'b00100;
      5'b01000:LCD_XX=5'b01000;
      5'b10000:LCD_XX=5'b10000;
      endcase
      
   end



//always @(LCD_XX)

//begin

  
   //case(LCD_XX)
      //3'b000: begin
      							
/*LCD_TEST_initial u0(.iCLK(CLOCK_50),
                    .iRST_N(DLY_RST),
                    .LCD_DATA(LCD_DATA),
                    .LCD_RW(LCD_RW),
                    .LCD_EN(LCD_EN),
                    .LCD_RS(LCD_RS));*/
				//end
	/*  3'b001: begin
      							
                 LCD_TEST_open 			u1	(	//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),		
							//	LCD Side
							.LCD_DATA(LCD_DATA),
							.LCD_RW(LCD_RW),
							.LCD_EN(LCD_EN),
							.LCD_RS(LCD_RS)	);
				end
	 3'b010: begin
      							
                 LCD_TEST_wrong 			u2	(	//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),		
							//	LCD Side
							.LCD_DATA(LCD_DATA),
							.LCD_RW(LCD_RW),
							.LCD_EN(LCD_EN),
							.LCD_RS(LCD_RS)	);
				end
	    3'b011: begin
      							
                 LCD_TEST_systemlocked 			u3	(	//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),		
							//	LCD Side
							.LCD_DATA(LCD_DATA),
							.LCD_RW(LCD_RW),
							.LCD_EN(LCD_EN),
							.LCD_RS(LCD_RS)	);
				end
		 3'b100: begin
      							
                 LCD_TEST_welcomlocked 			u4	(	
							//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),		
							//	LCD Side
							.LCD_DATA(LCD_DATA),
							.LCD_RW(LCD_RW),
							.LCD_EN(LCD_EN),
							.LCD_RS(LCD_RS)	);
				end*/
/*		 3'b000: begin
      							
                 LCD_TEST 			u5	(	//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),		
							//	LCD Side
							.LCD_DATA(LCD_DATA),
							.LCD_RW(LCD_RW),
							.LCD_EN(LCD_EN),
							.LCD_RS(LCD_RS)	);
				end*/
				//endcase
//end

endmodule